Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents

5.2.1. Clocking Options

Intel recommends two clocking options that you can use as reference for clock routing from IOPLLs to DIB instances.

Clocking Option 1

All three DIB subsystems are clocked by a single IOPLL.

The clock network for this option is larger because the network spans across the die height.

Advantages of this clock option:
  • The divergence point is closer to the DIB subsystem because it is from a single PLL.
  • For timing closure, you need to account for clock uncertainties from the divergence point to the leaf.
  • No clock uncertainties occur when using multiple IOPLLs.
Figure 13. DIB Clocking Option 1

Clocking Option 2

Each DIB subsystem is clocked by its own PLL.

This option is more efficient if the logic clocked by one IOPLL is not required to interact with the logic clocked by another IOPLL. Cross-PLL interactions incur larger clock uncertainties.

If a DIB subsystem (or even a few channels) is mutually exclusive with the other sections of logic or another DIB subsystem, you can use multiple IOPLLs to clock the logic driven by those unique clock domains.
  • In this case, the clock network span from the divergence point to the leaves is shorter because the network does not need to span across the die height.
  • This option also incurs less clock uncertainties.
Figure 14. DIB Clocking Option 2

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