Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

ID 683142
Date 3/18/2021
Document Table of Contents

8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide

Document Version Intel® Quartus® Prime Version Intel® FPGA IP Version Changes
2021.03.18 20.2 19.3.0 Updated the description for periphery-to-core transfer (RX side) in Table: Timing Transfer for TDM Modes.
2020.12.07 20.2 19.3.0
  • Updated the Synchronous Mode section.
  • Removed the Same Rate Synchronous Mode section.
2020.08.30 20.2 19.3.0
  • Edited the bits information for banks 1 and 2 in the AUX Channel Settings and Die-to-Die Mapping sections. Each bank is 16 data bits wide and includes an additional wire for clock.
2020.06.30 20.2 19.3.0 Initial release.

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