1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
5.2.2. Clock Synchronization
Intel recommends you to follow the board design guidelines for clock synchronization.
DUT Clock Synchronization between 2 Intel® Stratix® 10 GX 10M Dies
To synchronize the DUT reference clock, Intel recommends 20 ps.
DIB/System Clock Synchronization between 2 Intel® Stratix® 10 GX 10M Dies
The DIB clock and the system clock on the DIB RX side derive from the source synchronous clock on the TX side.
- The DIB clock on the DIB RX channel operates at the same frequency as the DIB clock on the DIB TX channel.
- The system clock on the RX dies is a divided clock from the source synchronous DIB clock to match the frequency of the system clock on the TX die. The clock divider supports division by 1 up to 16.
Note: The duty cycle is 60:40 for the odd divider, and you need to consider this duty cycle if any negative-edge flops are used.
- The TX version and RX version of the system clock on the same die are not synchronous because the clocks are from different IOPLLs on different dies.
Figure 15. Clocking Synchronization Using Different IOPLLs
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