4.3. Parameterizing and Generating the IP
Refer to DIB Intel Stratix 10 FPGA IP Parameters for the IP parameter values and description.
- In the IP Catalog (Tools > IP Catalog > Miscellaneous), locate and double-click the Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP.
- Specify a top-level name for your custom IP variation. This name identifies the IP variation files in your project. If prompted, also specify the target Intel® FPGA device family and output file HDL preference. Click OK.
- After parameterizing the IP, go to the Example Design tab and click Generate Example Design to create the simulation testbench. Skip to 5 if you do not want to generate the design example.
- Set a name for your <example_design_directory> and click OK to generate supporting files and scripts.
The testbench and scripts are located in the <example_design_directory>/simulation folder.
- Click Finish or Generate HDL to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .ip, .qip or .qsys IP variation file and HDL files for synthesis and simulation.
The top-level IP variation is added to the current Intel® Quartus® Prime project. Click Project > Add/Remove Files in Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.
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