Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

ID 683142
Date 3/18/2021
Public
Document Table of Contents

2.3. DIB Intel® Stratix® 10 FPGA IP Features

The DIB Intel® Stratix® 10 FPGA IP offers three modes of operation: Bypass, Asynchronous, and Synchronous.

The DIB Intel® Stratix® 10 FPGA IP includes the following features:

  • Time-division multiplexing (TDM) ratio
    • Asynchronous mode: 1:1, 2:1, or 4:1
    • Synchronous mode: 1:1, 2:1, or 4:1
  • Maximum transfer clock rate of 400 MHz (Asynchronous and Synchronous modes)
  • Bypass transfer latency of 2.5 ns (through direct interface bus only)
  • Three subsystems; each subsystem consists of 24 standard channels and 1 AUX channel
  • Four banks per channel
  • Maximum 22 I/Os per bank for Bypass mode and 20 I/Os for Asynchronous and Synchronous modes
  • Read and Write I/Os set per bank
Table 6.  Total I/Os Available
Mode TDM Ratio Total I/Os
Bypass Not applicable 6,564
Asynchronous or Synchronous 1:1 5,760
2:1 11,520
4:1 23,040

Did you find the information on this page useful?

Characters remaining:

Feedback Message