Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents

3.1.1. AUX Channel Settings

You can enable any combination settings for the AUX channel with certain restrictions.

Follow these restrictions:

  • Banks 0 and 3 are 22 bits wide and configurable as TX or RX.
  • Bank 1 has a total width of 17 bits:
    • 16 bits are for TX data only
    • 1 bit is reserved for clock
  • Bank 2 has a total width of 17 bits:
    • 16 bits are for RX data only
    • 1 bit is reserved for clock
Figure 6. AUX Channel Settings

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