Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

ID 683142
Date 3/18/2021
Public
Document Table of Contents
Give Feedback

6.1. DIB Intel® Stratix® 10 FPGA IP Clocks

The DIB Intel® Stratix® 10 FPGA IP mainly uses four clock signals.
Table 9.  Clocks
Signals Direction Description Mode
Bypass Asynchronous Synchronous
dib_clk Input Clocks the inter-die logic. Tie this signal high (not used). Tie to the DIB clock (used for TX banks). Tie to the DIB clock (used for TX banks).
sys_clk Input Ratio to the dib_clk signal set to Hard TDM ratio. Drives the soft TDM interface logic to the DIB Interface IP. Tie this signal high (not used). Tie this signal high (not used). Tie this signal to the same PLL source as the DIB clock ratio set to the Hard TDM ratio (used for TX banks).
dut_clk Input Input clock for the standard DIB channel. Tie this signal high (not used). Tie this signal to the DUT clock (synchronous to the DIB clock). Tie this signal high (not used).
Input clock for the AUX DIB channel. Tie this signal to the DUT clock (used for TX banks). Not applicable. Not applicable.
rem_clk Output Output clock for the standard DIB channel. Not used. Not used. Divided version of the DIB clock forwarded for the TX die (used as system clock on the RX banks).
Output clock for the AUX DIB channel. DUT clock forwarded from the TX die. Not applicable. Not applicable.