Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
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6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals

The DIB Intel® Stratix® 10 FPGA IP uses the DIB control, data and DIB pad signals.
Table 10.  Control Signals
Signal Width Direction Description
iopll_locked 1 Input

When you set the DIB Channel Type parameter to Standard Channel, this signal connects to locked IOPLL when using a bank with TDM.

This signal is not applicable if you select AUX Channel.

dib_ready_n 1 Output This signal goes low when the DIB channel is ready.
Table 11.  DIB Pad Signals
Signal Width Direction Description
dib_pad_0 24 Input/Output

DIB pads for bank 0.

The direction of this signal depends on the mode of I/O bank 0.

dib_pad_1 24 Input/Output

DIB pads for bank 1.

The direction of this signal depends on the mode of I/O bank 1.

dib_pad_2 24 Input/Output

DIB pads for bank 2.

The direction of this signal depends on the mode of I/O bank 2.

dib_pad_3 24 Input/Output

DIB pads for bank 3.

The direction of this signal depends on the mode of I/O bank 3.

Table 12.  DIB RX Data Signals
Signal Width Direction Description
core_rx_data_0 82 Output

Core data RX interface for bank 0.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_1 82 Output

Core data RX interface for bank 1.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_2 82 Output

Core data RX interface for bank 2.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_3 82 Output

Core data RX interface for bank 3.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

Table 13.  DIB TX Data Signals
Signal Width Direction Description
core_rx_data_0 82 Input

Core data TX interface for bank 0.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_1 82 Input

Core data TX interface for bank 1.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_2 82 Input

Core data TX interface for bank 2.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_3 82 Input

Core data TX interface for bank 3.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

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