Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
2. About the DIB Intel® Stratix® 10 FPGA IP x
2.1. Release Information 2.2. Device Support for DIB Intel® Stratix® 10 FPGA IP 2.3. DIB Intel® Stratix® 10 FPGA IP Features 2.4. Latency
3. Functional Description x
3.1. Bypass Mode 3.2. Asynchronous Mode 3.3. Synchronous Mode
3.1. Bypass Mode x
3.1.1. AUX Channel Settings
4. Creating and Parameterizing the Intel FPGA IP x
4.1. IP Catalog and Parameter Editor 4.2. Creating a New Intel® Quartus® Prime Project 4.3. Parameterizing and Generating the IP 4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design 4.5. Programming an FPGA Device
5. Designing with the DIB Intel® Stratix® 10 FPGA IP x
5.1. Reset Architecture 5.2. Clocking in Asynchronous and Synchronous Modes 5.3. Timing Closure 5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
5.2. Clocking in Asynchronous and Synchronous Modes x
5.2.1. Clocking Options 5.2.2. Clock Synchronization
5.3. Timing Closure x
5.3.1. Timing Transfer for Bypass Mode 5.3.2. Timing Transfer for TDM Modes
6. DIB Intel® Stratix® 10 FPGA IP Interface x
6.1. DIB Intel® Stratix® 10 FPGA IP Clocks 6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel

5.3.1. Timing Transfer for Bypass Mode

In the Bypass mode use case, two different dies, to a respective IOPLL, share a single reference clock.

Each PLL has the same frequency output clock configuration and the respective counters are synchronous in each die. The same frequency allows the data to be transferred synchronously from the clock in one die to the clock in the other die. However, the variations in the dies may affect how well the clocks in each die align with each other.

To analyze each die separately, consider these factors:
  • The clock uncertainty of one die relative to the clock on the other die must be computed.
  • The available data uncertainty for the transfer across the two dies and the link must be computed and budgeted for each die. For example, you may divide the uncertainty up to 40% for each die and 20% for the link.
Given these two factors, you may now create the appropriate SDC constraints for each die so that the Intel® Quartus® Prime Pro Edition software can close timing for each die independently.
  • For the TX die, create a virtual clock that has the clock uncertainty of the RX die, and then set the appropriate set_output_delay -max and set_output_delay -min constraints relative to the virtual clock that encompasses the link and data uncertainty in the other die.
  • For the RX die, set the appropriate set_input_delay -max and set_input_delay -min constraints.

With these SDC constraints, the Intel® Quartus® Prime Pro Edition software places and routes the DIB-to-core and core-to-DIB connections to meet the timing requirements.

Note: Intel provides the information to determine the clock and data uncertainties because the Timing Analyzer in the Intel® Quartus® Prime software would not have the information.
Figure 16. Timing Closure for Bypass Mode
Level Two Title