Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

ID 683142
Date 3/18/2021
Document Table of Contents

5.3.1. Timing Transfer for Bypass Mode

In the Bypass mode use case, two different dies, to a respective IOPLL, share a single reference clock.

Each PLL has the same frequency output clock configuration and the respective counters are synchronous in each die. The same frequency allows the data to be transferred synchronously from the clock in one die to the clock in the other die. However, the variations in the dies may affect how well the clocks in each die align with each other.

To analyze each die separately, consider these factors:
  • The clock uncertainty of one die relative to the clock on the other die must be computed.
  • The available data uncertainty for the transfer across the two dies and the link must be computed and budgeted for each die. For example, you may divide the uncertainty up to 40% for each die and 20% for the link.
Given these two factors, you may now create the appropriate SDC constraints for each die so that the Intel® Quartus® Prime Pro Edition software can close timing for each die independently.
  • For the TX die, create a virtual clock that has the clock uncertainty of the RX die, and then set the appropriate set_output_delay -max and set_output_delay -min constraints relative to the virtual clock that encompasses the link and data uncertainty in the other die.
  • For the RX die, set the appropriate set_input_delay -max and set_input_delay -min constraints.

With these SDC constraints, the Intel® Quartus® Prime Pro Edition software places and routes the DIB-to-core and core-to-DIB connections to meet the timing requirements.

Note: Intel provides the information to determine the clock and data uncertainties because the Timing Analyzer in the Intel® Quartus® Prime software would not have the information.
Figure 16. Timing Closure for Bypass Mode