Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents
Document Table of Contents
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
2. About the DIB Intel® Stratix® 10 FPGA IP
2.1. Release Information 2.2. Device Support for DIB Intel® Stratix® 10 FPGA IP 2.3. DIB Intel® Stratix® 10 FPGA IP Features 2.4. Latency
3. Functional Description
3.1. Bypass Mode 3.2. Asynchronous Mode 3.3. Synchronous Mode
3.1. Bypass Mode
3.1.1. AUX Channel Settings
4. Creating and Parameterizing the Intel FPGA IP
4.1. IP Catalog and Parameter Editor 4.2. Creating a New Intel® Quartus® Prime Project 4.3. Parameterizing and Generating the IP 4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design 4.5. Programming an FPGA Device
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
5.1. Reset Architecture 5.2. Clocking in Asynchronous and Synchronous Modes 5.3. Timing Closure 5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
5.2. Clocking in Asynchronous and Synchronous Modes
5.2.1. Clocking Options 5.2.2. Clock Synchronization
5.3. Timing Closure
5.3.1. Timing Transfer for Bypass Mode 5.3.2. Timing Transfer for TDM Modes
6. DIB Intel® Stratix® 10 FPGA IP Interface
6.1. DIB Intel® Stratix® 10 FPGA IP Clocks 6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel

5.3.2. Timing Transfer for TDM Modes

There are three types of timing transfer in TDM modes.
Figure 17. Timing Closure for TDM Mode
Table 8.  Timing Transfer for TDM Modes
Timing Transfer Description
Core-to-periphery transfer (TX side)

A synchronous transfer from the system clock with a flop in the core to the DIB clock with a flop in the periphery on the same die.

The Timing Analyzer in the Intel® Quartus® Prime software analyzes this path as a regular path.

Die-to-die transfer

Intel determines the timing closure for this path.

Periphery-to-core transfer (RX side)

A transfer from the DIB clock from the RX die to the system clock on the RX die.

For SYNC mode only: The Timing Analyzer in the Intel® Quartus® Prime software analyzes this path as a regular path.

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