5.3.2. Timing Transfer for TDM Modes
|Core-to-periphery transfer (TX side)||
A synchronous transfer from the system clock with a flop in the core to the DIB clock with a flop in the periphery on the same die.
The Timing Analyzer in the Intel® Quartus® Prime software analyzes this path as a regular path.
Intel determines the timing closure for this path.
|Periphery-to-core transfer (RX side)||
A transfer from the DIB clock from the RX die to the system clock on the RX die.
For SYNC mode only: The Timing Analyzer in the Intel® Quartus® Prime software analyzes this path as a regular path.
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