Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide
ID
683142
Date
3/18/2021
Public
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel
5.3.2. Timing Transfer for TDM Modes
There are three types of timing transfer in TDM modes.
Figure 17. Timing Closure for TDM Mode
Timing Transfer | Description |
---|---|
Core-to-periphery transfer (TX side) | A synchronous transfer from the system clock with a flop in the core to the DIB clock with a flop in the periphery on the same die. The Timing Analyzer in the Intel® Quartus® Prime software analyzes this path as a regular path. |
Die-to-die transfer | Intel determines the timing closure for this path. |
Periphery-to-core transfer (RX side) | A transfer from the DIB clock from the RX die to the system clock on the RX die. For SYNC mode only: The Timing Analyzer in the Intel® Quartus® Prime software analyzes this path as a regular path. |