Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
2. About the DIB Intel® Stratix® 10 FPGA IP x
2.1. Release Information 2.2. Device Support for DIB Intel® Stratix® 10 FPGA IP 2.3. DIB Intel® Stratix® 10 FPGA IP Features 2.4. Latency
3. Functional Description x
3.1. Bypass Mode 3.2. Asynchronous Mode 3.3. Synchronous Mode
3.1. Bypass Mode x
3.1.1. AUX Channel Settings
4. Creating and Parameterizing the Intel FPGA IP x
4.1. IP Catalog and Parameter Editor 4.2. Creating a New Intel® Quartus® Prime Project 4.3. Parameterizing and Generating the IP 4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design 4.5. Programming an FPGA Device
5. Designing with the DIB Intel® Stratix® 10 FPGA IP x
5.1. Reset Architecture 5.2. Clocking in Asynchronous and Synchronous Modes 5.3. Timing Closure 5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
5.2. Clocking in Asynchronous and Synchronous Modes x
5.2.1. Clocking Options 5.2.2. Clock Synchronization
5.3. Timing Closure x
5.3.1. Timing Transfer for Bypass Mode 5.3.2. Timing Transfer for TDM Modes
6. DIB Intel® Stratix® 10 FPGA IP Interface x
6.1. DIB Intel® Stratix® 10 FPGA IP Clocks 6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel

5.2. Clocking in Asynchronous and Synchronous Modes

The DIB subsystem requires the fabric clock, sourced from an IOPLL to clock the DIB subsystem.

The DIB subsystem does not have any PLLs, therefore the clocks come from IOPLLs.

The DIB subsystem sends a source synchronous clock to another DIB subsystem in the adjacent die (TX or RX). In Synchronous mode, the system clock is synchronous to the DIB clock.

Both the system clock (if applicable) and the DIB clock should be derived from the same IOPLL output, and routed to the DCM (core clock multiplexer) nearest to the DIB subsystem,
  • The DCM has a divider that does the division of 1, 2, or 4.
  • Sharing the same clock and using the divider within the DCM reduces clock uncertainties.

Each Intel® Stratix® 10 GX 10M die contains 24 IOPLLs and you can program each IOPLL to produce nine unique clocks (divided from the PLL's VCO).

On the receiving die, the DIB clock and system clock (if applicable) on the DIB RX core is derived from the source synchronous clock in the DIB TX core.
  • The DIB clock on the RX side runs at the same frequency as the DIB clock on the TX side.
  • The DIB clock goes through the clock divider inside the DIB to generate the rem_clk port on the RX die.
Each DIB channel has its own independent system clock and associated DIB clock.
  • The smallest granularity for the clock domain is per channel.
  • The Intel® Stratix® 10 GX 10M variant parts per die has a total of 72 clock domains for the system clock and DIB clock.
Note: Intel recommends that each channel should not have its own unique clock source at the die level to reduce clock uncertainties.

Section Content
Clocking Options
Clock Synchronization

Level Two Title