Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

ID 683142
Date 3/18/2021
Document Table of Contents

5.2. Clocking in Asynchronous and Synchronous Modes

The DIB subsystem requires the fabric clock, sourced from an IOPLL to clock the DIB subsystem.

The DIB subsystem does not have any PLLs, therefore the clocks come from IOPLLs.

The DIB subsystem sends a source synchronous clock to another DIB subsystem in the adjacent die (TX or RX). In Synchronous mode, the system clock is synchronous to the DIB clock.

Both the system clock (if applicable) and the DIB clock should be derived from the same IOPLL output, and routed to the DCM (core clock multiplexer) nearest to the DIB subsystem,
  • The DCM has a divider that does the division of 1, 2, or 4.
  • Sharing the same clock and using the divider within the DCM reduces clock uncertainties.

Each Intel® Stratix® 10 GX 10M die contains 24 IOPLLs and you can program each IOPLL to produce nine unique clocks (divided from the PLL's VCO).

On the receiving die, the DIB clock and system clock (if applicable) on the DIB RX core is derived from the source synchronous clock in the DIB TX core.
  • The DIB clock on the RX side runs at the same frequency as the DIB clock on the TX side.
  • The DIB clock goes through the clock divider inside the DIB to generate the rem_clk port on the RX die.
Each DIB channel has its own independent system clock and associated DIB clock.
  • The smallest granularity for the clock domain is per channel.
  • The Intel® Stratix® 10 GX 10M variant parts per die has a total of 72 clock domains for the system clock and DIB clock.
Note: Intel recommends that each channel should not have its own unique clock source at the die level to reduce clock uncertainties.

Did you find the information on this page useful?

Characters remaining:

Feedback Message