5.2. Clocking in Asynchronous and Synchronous Modes
The DIB subsystem does not have any PLLs, therefore the clocks come from IOPLLs.
The DIB subsystem sends a source synchronous clock to another DIB subsystem in the adjacent die (TX or RX). In Synchronous mode, the system clock is synchronous to the DIB clock.
- The DCM has a divider that does the division of 1, 2, or 4.
- Sharing the same clock and using the divider within the DCM reduces clock uncertainties.
Each Intel® Stratix® 10 GX 10M die contains 24 IOPLLs and you can program each IOPLL to produce nine unique clocks (divided from the PLL's VCO).
- The DIB clock on the RX side runs at the same frequency as the DIB clock on the TX side.
- The DIB clock goes through the clock divider inside the DIB to generate the rem_clk port on the RX die.
- The smallest granularity for the clock domain is per channel.
- The Intel® Stratix® 10 GX 10M variant parts per die has a total of 72 clock domains for the system clock and DIB clock.
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