Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

ID 683142
Date 3/18/2021
Document Table of Contents

5.1. Reset Architecture

The DIB subsystem is either in freeze mode or user mode.

Upon power-up, the DIB subsystem enters freeze mode. All the freeze signals from the DIB subsystem get asserted when the system asserts the power-on reset signal. During freeze mode, the DIB subsystem is in a safe state and all interface signals to the core fabric are driven high.

During freeze mode, the DIB I/Os are tri-stated, and the DIB SSM configures the entire DIB subsystem.

For the Intel® Stratix® 10 GX 10M variant, the external reset is controlled by user logic or your system design.
  • You must track all the dib_ready pins from both dies to determine that both Intel® Stratix® 10 GX 10M variants are ready for data transactions.
  • You should enable the external reset only after all the dib_ready_n pins are asserted.
  • Only after enabling the external reset, you enable the cross-die transactions.

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