5.1. Reset Architecture
Upon power-up, the DIB subsystem enters freeze mode. All the freeze signals from the DIB subsystem get asserted when the system asserts the power-on reset signal. During freeze mode, the DIB subsystem is in a safe state and all interface signals to the core fabric are driven high.
During freeze mode, the DIB I/Os are tri-stated, and the DIB SSM configures the entire DIB subsystem.
- You must track all the dib_ready pins from both dies to determine that both Intel® Stratix® 10 GX 10M variants are ready for data transactions.
- You should enable the external reset only after all the dib_ready_n pins are asserted.
- Only after enabling the external reset, you enable the cross-die transactions.
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