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1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel
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4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design
Refer to the Designing with the DIB Intel Stratix 10 FPGA IP before compiling the DIB Intel® Stratix® 10 FPGA IP design.
To compile your design, click Start Compilation on the Processing menu in the Intel® Quartus® Prime software. You can use the generated .ip or .qip file to include relevant files into your project.
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