1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
For TDM modes, the latency for each TDM case includes the core-to-periphery and periphery-to-core timing closures for both TX and RX instances. The latency number does not include potential pipe stages needed to achieve a required maximum frequency. For bypass modes, the latency number includes only the latency across the DIB interface (hard wire).
|DIB Operation Mode||DIB Clock Frequency (MHz)||System/DUT Clock Frequency (MHz)||Hard TDM Ratio||DIB Clock/System Clock Ratio||DIB Pin-to-Pin Latency (ns) 1|
|Bypass||Not Applicable||Not Applicable||Not Applicable||Not Applicable||2.5|
1 Latency without pipe stage.
2 The latency depends on the pointer value of the hardened TDM, in DIB clock cycles; 1 cycle = 2.5 ns, 2 cycles = 5 ns, and so on.
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