Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
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2.4. Latency

For TDM modes, the latency for each TDM case includes the core-to-periphery and periphery-to-core timing closures for both TX and RX instances. The latency number does not include potential pipe stages needed to achieve a required maximum frequency. For bypass modes, the latency number includes only the latency across the DIB interface (hard wire).
Table 7.  Latency
DIB Operation Mode DIB Clock Frequency (MHz) System/DUT Clock Frequency (MHz) Hard TDM Ratio DIB Clock/System Clock Ratio DIB Pin-to-Pin Latency (ns) 1
Bypass Not Applicable Not Applicable Not Applicable Not Applicable 2.5
Synchronous 400 100 4:1 4:1 5–12.5 2
200 2:1 2:1 5–7.5 2
400 4:1 1:1 5
400 2:1 1:1 5
300 300 4:1 1:1 6.7
200 200 4:1 1:1 10
1 Latency without pipe stage.
2 The latency depends on the pointer value of the hardened TDM, in DIB clock cycles; 1 cycle = 2.5 ns, 2 cycles = 5 ns, and so on.

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