1.1. Intel® Stratix® 10 GX/SX Family Variants
Intel® Stratix® 10 devices are available in FPGA (GX) and SoC (SX) variants.
- Intel® Stratix® 10 GX devices deliver up to 1 GHz core fabric performance and contain up to 10.2 million LEs in the fabric. They also feature up to 96 general purpose transceivers on separate transceiver tiles, and 2666 Mbps DDR4 external memory interface performance. The transceivers are capable of up to 28.3 Gbps short reach and across the backplane. These devices are optimized for FPGA applications that require the highest transceiver bandwidth and core fabric performance, with the power efficiency of Intel’s 14 nm tri-gate process technology.
- Intel® Stratix® 10 SX devices have a feature set that is identical to Intel® Stratix® 10 GX devices, with the addition of an embedded quad-core 64 bit Arm* Cortex* A53 hard processor system.
Common to all Intel® Stratix® 10 family variants is a high-performance fabric based on the new Intel® Hyperflex™ core architecture that includes additional Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module (ALM) and a rich set of high performance building blocks including:
- M20K (20 Kb) embedded memory blocks
- Variable precision DSP blocks with hard IEEE 754 compliant floating-point units
- Fractional synthesis and integer PLLs
- Hard memory controllers and PHY for external memory interfaces
- General purpose IO cells
To clock these building blocks, Intel® Stratix® 10 devices use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while it is operating.
All family variants also contain high speed serial transceivers, containing both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols. In addition to the hard PCS, Intel® Stratix® 10 devices contain multiple instantiations of PCI Express* hard IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane configurations, and hard 10GBASE-KR/40GBASE-KR4 FEC for every transceiver. The hard PCS, FEC, and PCI Express IP free up valuable core logic resources, save power, and increase your productivity.