Stratix® 10 GX/SX Device Overview

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ID 683729
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 GX/SX Device Overview
1. Intel® Stratix® 10 GX/SX Device Overview x
1.1. Intel® Stratix® 10 GX/SX Family Variants 1.2. Innovations in Intel® Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Intel® Stratix® 10 Block Diagram 1.5. Intel® Stratix® 10 FPGA and SoC Family Plan 1.6. Intel® Hyperflex™ Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Intel® Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Intel® Stratix® 10 GX/SX Device Overview
1.1. Intel® Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Intel® Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 GX/SX Device Overview

1.2. Innovations in Intel® Stratix® 10 FPGAs and SoCs

Intel® Stratix® 10 FPGAs and SoCs deliver many significant improvements over the previous generation high-performance Stratix® V FPGAs.

Table 1.   Key Features of Intel® Stratix® 10 Devices Compared to Stratix® V Devices
Feature Stratix® V FPGAs Intel® Stratix® 10 FPGAs and SoCs
Process technology 28 nm TSMC (planar transistor) 14 nm Intel tri-gate (FinFET)
Hard processor core None Quad-core 64 bit Arm* Cortex* -A53 (SoC only)
Core architecture Conventional core architecture with conventional interconnect Intel® Hyperflex™ core architecture with Hyper-Registers in the interconnect
Core performance 500 MHz 1 GHz
Power dissipation 1x As low as 0.3x
Logic density 952 KLE 10,200 KLE
Embedded memory (M20K) 52 Mbits 253 Mbits
18x19 multipliers 3,926
Note: Multiplier is 18x18 in Stratix® V devices.
11,520
Note: Multiplier is 18x19 in Intel® Stratix® 10 devices.
Floating point DSP capability Up to 1 TFLOP, requires soft floating point adder and multiplier Up to 10 TFLOP, hard IEEE 754 compliant single precision floating point adder and multiplier
Maximum transceivers 66 96
Maximum transceiver data rate (chip-to-chip) 28.05 Gbps

26.6 Gbps L-Tile

28.3 Gbps H-Tile
Maximum transceiver data rate (backplane) 12.5 Gbps

12.5 Gbps L-Tile

28.3 Gbps H-Tile
Hard memory controller None

DDR4 @ 1333 MHz/2666 Mbps

DDR3 @ 1067 MHz/2133 Mbps
Hard protocol IP PCIe* Gen3 x8 (up to 4 instances)

PCIe* Gen3 x16 (up to 4 instances)

SR-IOV (4 physical functions / 2k virtual functions) on H-Tile devices

10GBASE-KR/40GBASE-KR4 FEC
Core clocking and PLLs Global, quadrant and regional clocks supported by fractional-synthesis fPLLs Programmable clock tree synthesis supported by fractional synthesis fPLLs and integer IO PLLs
Register state readback and writeback Not available Non-destructive register state readback and writeback for ASIC prototyping and other applications (supported in Intel® Stratix® 10 GX 10M devices only)

These innovations result in the following improvements:

  • Improved Core Logic Performance: The Intel® Hyperflex™ core architecture combined with 14 nm Intel tri-gate technology allows Intel® Stratix® 10 devices to achieve 2X the core performance compared to the previous generation
  • Lower Power:  Intel® Stratix® 10 devices use up to 70% lower power compared to the previous generation, enabled by 14 nm Intel tri-gate technology, the Intel® Hyperflex™ core architecture, and optional power saving features built into the architecture
  • Higher Density: Intel® Stratix® 10 devices offer three times the level of integration, with up to 10.2 million logic elements (LEs), over 253 Mbits of embedded memory blocks (M20K), and 11,520 18x19 multipliers
  • Embedded Processing: Intel® Stratix® 10 SoCs feature a Quad-Core 64 bit Arm* Cortex* -A53 processor optimized for power efficiency and software compatible with previous generation Arria® and Cyclone® SoC devices
  • Improved Transceiver Performance: With up to 96 transceiver channels implemented in heterogeneous 3D SiP transceiver tiles, Intel® Stratix® 10 GX and SX devices support data rates up to 28.3 Gbps chip-to-chip and 28.3 Gbps across the backplane with signal conditioning circuits capable of equalizing over 30 dB of system loss
  • Improved DSP Performance: The variable precision DSP block in Intel® Stratix® 10 devices features hard fixed and floating point capability, with up to 10 TFLOP IEEE754 single-precision floating point performance
  • Additional Hard IP: Intel® Stratix® 10 devices include many more hard IP blocks than previous generation devices, with a hard memory controller included in each bank of 48 general purpose IOs, a hard PCIe* Gen3 x16 full protocol stack in each transceiver tile, and a hard 10GBASE-KR/40GBASE-KR4 FEC in every transceiver channel
  • Enhanced Core Clocking: Intel® Stratix® 10 devices feature programmable clock tree synthesis; clock trees are only synthesized where needed, increasing the flexibility and reducing the power dissipation of the clocking solution
  • Additional Core PLLs: The core fabric in Intel® Stratix® 10 devices is supported by both integer IO PLLs and fractional synthesis fPLLs, resulting in a greater total number of PLLs available than the previous generation
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