Intel® Stratix® 10 GX/SX Device Overview

ID 683729
Date 8/18/2022
Document Table of Contents

1.13. Adaptive Logic Module (ALM)

Intel® Stratix® 10 devices use a similar adaptive logic module (ALM) as the previous generation Intel® Arria® 10 and Stratix® V FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the devices.

The ALM block diagram shown in the following figure has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers.

Figure 11.  Intel® Stratix® 10 FPGA and SoC ALM Block Diagram

Key features and capabilities of the ALM include:

  • High register count with 4 registers per 8-input fracturable LUT, operating in conjunction with the new Intel® Hyperflex™ architecture, enables Intel® Stratix® 10 devices to maximize core performance at very high core logic utilization
  • Implements select 7-input logic functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core logic utilization

The Intel® Quartus® Prime software takes advantage of the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Intel® Quartus® Prime software simplifies design reuse as it automatically maps legacy designs into the Intel® Stratix® 10 ALM architecture.

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