Stratix® 10 GX/SX Device Overview

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ID 683729
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 GX/SX Device Overview
1. Intel® Stratix® 10 GX/SX Device Overview x
1.1. Intel® Stratix® 10 GX/SX Family Variants 1.2. Innovations in Intel® Stratix® 10 FPGAs and SoCs 1.3. FPGA and SoC Features Summary 1.4. Intel® Stratix® 10 Block Diagram 1.5. Intel® Stratix® 10 FPGA and SoC Family Plan 1.6. Intel® Hyperflex™ Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Intel® Stratix® 10 Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Interlaken PCS Hard IP 1.11. 10G Ethernet Hard IP 1.12. External Memory and General Purpose I/O 1.13. Adaptive Logic Module (ALM) 1.14. Core Clocking 1.15. Fractional Synthesis PLLs and I/O PLLs 1.16. Internal Embedded Memory 1.17. Variable Precision DSP Block 1.18. Hard Processor System (HPS) 1.19. Power Management 1.20. Device Configuration and Secure Device Manager (SDM) 1.21. Device Security 1.22. Configuration via Protocol Using PCI Express* 1.23. Partial and Dynamic Reconfiguration 1.24. Fast Forward Compile 1.25. Single Event Upset (SEU) Error Detection and Correction 1.26. Document Revision History for the Intel® Stratix® 10 GX/SX Device Overview
1.1. Intel® Stratix® 10 GX/SX Family Variants x
1.1.1. Available Options
1.8. Intel® Stratix® 10 Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.18. Hard Processor System (HPS) x
1.18.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 GX/SX Device Overview

1.16. Internal Embedded Memory

Intel® Stratix® 10 devices contain two types of embedded memory blocks: M20K (20 Kb) and MLAB (640 bit).

The M20K and MLAB blocks are familiar block sizes carried over from previous Intel device families. The MLAB blocks are ideal for wide and shallow memories, while the M20K blocks are intended to support larger memory configurations and include hard ECC. Both M20K and MLAB embedded memory blocks can be configured as a single-port or dual-port RAM, FIFO, ROM, or shift register. These memory blocks are highly flexible and support a number of memory configurations as shown in the following table.

Table 10.  Internal Embedded Memory Block Configurations

MLAB (640 bits)

M20K (20 Kb)

64 x 10 (supported through emulation)

32 x 20

2K x 10 (or x8)

1K x 20 (or x16)

512 x 40 (or x32)

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