Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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4.3.4. Timing Constraints

When you configure the PHY in 1G/2.5G configuration, Intel® recommends that you refer to the Timing Constraints section of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide for details on the timing constraint examples.

When the IEEE 1588v2 feature is enabled for 1G/2.5G PHY configuration, add the following constraints to the timing constraint file:

  • Set false path from native PHY 1G clock to 2.5G 1588 logic and vice versa. Since the 2.5G 1588 logic is not running the native 1G clock, you do not need to ensure timing closure for LL 10GbE MAC data path at 1G clock. For example:
    set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|*}] \
                   -to   [get_registers {*|alt_mge_1588_tod_2p5g:*|* \
                                         *|alt_mge_1588_tod_sync_*_2p5g:*|*}]
    set_false_path -from [get_registers {*|alt_mge_1588_tod_2p5g:*|* \
                                         *|alt_mge_1588_tod_sync_*_2p5g:*|*}] \
                   -to   [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|*}] 
    where the path indicated by profile0 is associated to the native PHY 1G clock, whereas the alt_mge_1588_tod_2p5g and alt_mge_1588_tod_sync_*_2p5g paths indicate the 2.5G 1588 logic.
  • Set false path from native PHY 2.5G clock to 1G 1588 logic and vice versa. Since the 1G 1588 logic is not running the native 2.5G clock, you do not need to ensure timing closure for LL 10GbE MAC data path at 2.5G clock. For example:
    set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}] \
                   -to   [get_registers {*|alt_mge_1588_tod_1g:*|* \
                                         *|alt_mge_1588_tod_sync_*_1g:*|*}]
    set_false_path -from [get_registers {*|alt_mge_1588_tod_1g:*|* \
                                         *|alt_mge_1588_tod_sync_*_1g:*|*}] \
                   -to   [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}]
    
    where the path indicated by profile1 is associated to the native PHY 2.5G clock, whereas the alt_mge_1588_tod_1g and alt_mge_1588_tod_sync_*_1g paths indicate the 1G 1588 logic.