Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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7.8. ToD Interface Signals

Table 26.  ToD Interface Signal
Signal Direction Width Description
master_pulse_per_second Out 1 Pulse per second (PPS) from the master PPS module. The signal stay asserted for 10 ms.
start_tod_sync[] In [NUM_CHANNELS] Use this signal to trigger the ToD synchronization process. The time of day of the local ToD is synchronized to the time of day of the master ToD. The synchronization process continues as long as this signal remains asserted.
pulse_per_second_10g[] Out [NUM_CHANNELS] PPS from the 10G PPS module of channel n. The signal stay asserted for 10 ms.
pulse_per_second_1g[] Out [NUM_CHANNELS] PPS from the 1G PPS module of channel n. The signal stay asserted for 10 ms.