Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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7.7. Packet Classifier Interface Signals

Table 25.  Packet Classifier Interface Signals
Signal Direction Width Description
tx_egress_timestamp_request_ in_valid[] In [NUM_CHANNELS] Assert this signal to request timestamping for the TX frame. This signal must be asserted in the same clock cycle avalon_st_tx_startofpacket is asserted.
tx_egress_timestamp_request_ in_fingerprint[][] In [NUM_CHANNELS][TSTAMP_ FP_WIDTH] Use this bus to specify the fingerprint that validates the timestamp for the incoming packet.
clock_operation_mode_mode[][] In [NUM_CHANNELS][2] Use this signal to specify the clock mode.
  • 00: Ordinary clock
  • 01: Boundary clock
  • 10: End to end transparent clock
  • 11: Peer to peer transparent clock
pkt_with_crc_mode[] In [NUM_CHANNELS] Use this signal to specify whether or not a packet contains CRC.
  • 0: Packet contains CRC
  • 1: Packet does not contain CRC
tx_ingress_timestamp_valid[] In [NUM_CHANNELS] Indicates whether or not the residence time can be updated.
  • 0: Prevents update for residence time
  • 1: Allows update for residence time based on decoded results

When this signal is deasserted, the tx_etstamp_ins_ctrl_out_residence_ti me_update signal also gets deasserted.

tx_ingress_timestamp_96b_ data[][] In [NUM_CHANNELS][96] 96-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_64b_ data[][] In [NUM_CHANNELS][64] 64-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_format[] In [NUM_CHANNELS] The format of the timestamp for calculating the residence time.
  • 0: 96 bits
  • 1: 64 bits

This signal must be aligned to the start of an incoming packet.