Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
Public
Download
Document Table of Contents

1.2.2. Design Example Parameters

Table 2.  Parameters in the Example Design Tab
Parameter Description
Select Design Available example designs for the IP parameter settings. When you select an example design from the Preset library, this field shows the selected design.
Example Design Files

The files to generate for the different development phase.

  • Simulation—generates the necessary files for simulating the example design.
  • Synthesis—generates the synthesis files. Use these files to compile the design in the Intel® Quartus® Prime Pro Edition software for hardware testing and perform static timing analysis.
Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is not available, there is no supported board for the options that you select.

Stratix 10 GX Signal Integrity H-Tile (Prod) Development Kit : This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device to match the device on the Intel® FPGA IP development kit. If your board revision has a different device grade, you can change the target device.

Custom Development Kit: This option allows you to test the design example on a third party development kit with Intel® FPGA IP device, a custom designed board with Intel® FPGA IP device, or a standard Intel® FPGA IP development kit not available for selection. You can also select a custom device for the custom development kit.

No Development Kit: This option excludes the hardware aspects for the design example.

Change Target Device Select this parameter to display and select all devices for the Intel® FPGA IP development kit.
Specify Number of Channels The number of Ethernet channels.

For Intel® Stratix® 10 devices, the default number of channels is 2 and this parameter is not selectable.

Analog Voltage VCCR_GXB and VCCT_GXB supply voltage for the Transceiver.
Note: This option is only available from Intel® Quartus® Prime Pro Edition version 17.0 onwards
Enable Native PHY Debug Master Endpoint (NPDME) Turn on this option to enable the Transceiver Native PHY Debug Master Endpoint (NPDME) feature.
Note: This option is only available from Intel® Quartus® Prime Pro Edition version 17.0 onwards