Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
Public
Download
Document Table of Contents

1.1. Directory Structure

Figure 2. Directory Structure for the Design Example
Table 1.  Directory and File Description
Directory/File Description
altera_eth_top.qpf Intel® Quartus® Prime Pro Edition project file.
altera_eth_top.qsf Intel® Quartus® Prime Pro Edition settings file.
altera_eth_top.sv Design example top-level HDL.
altera_eth_top.sdc Synopsys Design Constraints (SDC) file.
rtl The folder that contains the design example synthesizable components.

rtl/altera_eth_10g_mac_base_r.sv

rtl/altera_10g_mac_base_r_wrap.v

Design example DUT top-level files for 10GBASE-R Ethernet design example.

rtl/altera_mge_rd.sv

rtl/altera_mge_channel.v

Design example DUT top-level files for the following Ethernet design examples:
  • 1G/2.5G with 1588v2 feature
  • 1G/2.5G/10G with IEEE 1588v2 feature
  • 10M/100M/1G/2.5G/10G

rtl/altera_mge_multi_channel.sv

rtl/altera_mge_channel.v

Design example DUT top-level files for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example.
rtl/<Design Component> The folder for each synthesizable component including Platform Designer generated IPs, such as LL 10GbE MAC, PHY, and FIFO.
simulation/ed_sim/models The folder that contains the testbench files.

simulation/ed_sim/cadence

simulation/ed_sim/mentor

simulation/ed_sim/synopsys/vcs

simulation/ed_sim/xcelium

The folder that contains the simulation script. It also serves as a working area for the simulator.
hwtesting/system_console The folder that contains system console scripts for hardware testing.
output_files The folder that contains Intel® Quartus® Prime Pro Edition output files including Intel® Quartus® Prime Pro Edition compilation reports and design programing file (.sof file).