4.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
The simulation test case performs the following steps:
- Starts up the design example with an operating speed of 2.5G.
- Configures the MAC, PHY, and FIFO buffer for both channels.
- Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for each channel.
- Sends the following packets:
- No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
- VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
- No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
- VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
- Repeats steps 2 to 4 for 1G.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.