Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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3.4. Simulation

The simulation test case performs the following steps:

  1. Starts up the example design with an operating speed of 10 Gbps.
  2. Configures the MAC, PHY, and FIFO buffer for both channels.
  3. Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for both channels.
  4. Sends the following packets:
    • 64-byte packet
    • 1518-byte packet
    • 100-byte packet
  5. Repeats steps 2 to 4 for 2.5G, 1G, 100M, and 10M.

When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.