Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
Document Table of Contents

3. 10M/100M/1G/2.5G/10G Ethernet Design Example

The 10M/100M/1G/2.5G/10G Ethernet design example demonstrates an Ethernet solution for Intel® Stratix® 10 using the LL 10GbE MAC Intel® FPGA IP operating at 10M, 100M, 1G, 2.5G, and 10G.

Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor.