Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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6.3.1. Design Components

Table 16.  Design Components
Component Description
LL 10GbE MAC

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 10M/100M/1G/2.5G/5G/10G (USXGMII)
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • TX and RX datapath Reset/Default To Enable: Selected
  • Use legacy XGMII Interface: Not selected
  • Use legacy Avalon Memory-Mapped Interface: Not selected
  • Use legacy Avalon Streaming Interface: Selected
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
  • Enable time stamping: Selected
  • Enable PTP one-step clock support: Selected
  • Timestamp fingerprint width: 4
  • Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP with the following configuration:
  • Speed: 10M/100M/1G/2.5G/5G/10G
  • Enable SGMII bridge: Not selected
  • Enabled IEEE 1588 Precision Time Protocol: Selected
  • Connect to MGBASE-T PHY: Not selected
  • Connect to NBASE-T PHY: Selected
  • VCCR_GXB and VCC_GXB supply voltage for the Transceiver: 1_0V
  • Reference clock frequency for 10GbE (MHz): 644.53125
  • Enable Native PHY Debug Master Endpoint: Not selected
  • Enable capability registers: Not selected
  • Enable control and status registers: Not selected
  • Enable PRBS soft accumulators: Not selected
Channel address decoder Decodes the addresses of the components in each Ethernet channel, such as PHY and LL 10GbE MAC.
Multi-channel address decoder Decodes the addresses of the components used by all channels , such as the Master ToD module.
Top address decoder Decodes the addresses of the top-level components, such as the Traffic Controller.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP. Resets the transceiver.
ATX PLL Generates a TX serial clock for the Intel® Stratix® 10 transceiver.
Core fPLL Generates clocks for all design components.
Design Components for the IEEE 1588v2 Feature
ToD Sampling fPLL Generates the clocks for the 1588 design components.
Master ToD The master ToD for all channels.
ToD Synch Synchronizes the master ToD to all local ToDs.
Local ToD The ToD for each channel.
Master PPS The master PPS. Returns pulse per second (pps) for all channels.
PPS The slave PPS. Returns pulse per second (pps) for each channel.
PTP Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel® FPGA IP.