Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 2/16/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1. Features

  • Supports dual Ethernet channel operating at 10G using Intel® Stratix® 10 Native PHY.
  • On the transmit and receive paths:
    • Provides packet monitoring system.
    • Reports Ethernet MAC statistics counter.
  • Supports testing using different types of Ethernet packet transfer protocol.