Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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6.5. Hardware Testing

Follow the procedure at the provided link to test the design example in the selected hardware.

In the Clock Controller application, which is part of the development kit, set the following frequencies:

  • Y1—644.53125 MHz
  • U5, OUT 8—125 MHz