Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.01.11 21.2 19.3.0 Updated Figure: Clocking Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example to correct input and output clock for PLL.
2021.10.22 21.2 19.3.0
  • Updated reference to target device 1SX280HU1F50E2VG to 1SG280HU1F50E2VG.
  • Updated the description and steps to Changing Target Device in Hardware Design Example and Procedure in the Quick Start Guide chapter.
  • Removed references to NCSim simulator throughout the document.
2020.11.30 19.3 19.3.0 Updated the 10GBASE-R Ethernet Design Example chapter:
  • Updated Figure: Clocking and Reset Scheme for 10GBASE-R Design Example
  • Updated Figure: Interface Signals of the 10GBASE-R Ethernet Design Example
  • Updated for latest branding standards.
2020.09.28 19.3 19.3.0 Updated the 10GBASE-R Ethernet Design Example chapter:
  • Added new topics:
    • Configuring FIFO Depth for Avalon® Streaming Loopback.
    • Running Avalon® Streaming Loopback Test Case with Jumbo Ethernet Packets.
  • Updated the description for FIFO in Table: Design Components in the 10GBASE-R Ethernet Design Example chapter.
  • Made editorial edits throughout the document.
2020.06.30 19.3 19.3.0 Updated Figure: Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With IEEE 1588v2 Feature to correct the frequency values for latency_sclk, TOD clk_sampling, and tx_serial_clk.
2019.12.13 19.3 19.3.0
  • Added a note to the procedure steps in the Compiling and Simulating the Design section.
  • Added a new Topic—Updating PHY IP Design File Names.
  • Updated the procedure steps in the Changing Target Device in Hardware Design Example section.
  • Updated for latest Intel® branding standards.
2019.10.02 19.3 19.3.0
  • Added new topic—Changing Target Device in Hardware Design Example.
  • Updated references to Intel® Stratix® 10 GX Signal Integrity H-Tile (ES) Development Kit as Intel® Stratix® 10 GX Signal Integrity H-Tile (Production) Development Kit.
  • Updated the Generating the Design topic to add a note to Step 8.
  • Updated Figure: Example Design Tab.
  • Updated the Hardware and Software Requirements topics for all design example chapters
  • Updated Table: 1G/2.5G/5G/10G Multi-rate PHY Register Definitions.
2019.07.01 19.2 19.2.0
  • Updated all references to Stratix 10 H-Tile GX Transceiver Signal Integrity Development Kit to Stratix 10 GX Signal Integrity H-Tile (ES) Development Kit.
  • Updated Table: Parameters in the Example Design Tab:
    • Updated the parameter name Example Design Files for Simulation or Synthesis to Example Design Files.
    • Updated the parameter name Enable NPDME support to Enable Native PHY Debug Master Endpoint (NPDME).
  • Updated Figure: Example Design Tab.
  • Updated Table: Design Components of the 10GBASE-R Ethernet design example to update the description for FIFO.
  • Made editorial edits through out the document.
2019.04.30 19.1 19.1
  • Updated Table: Parameters in the Example Design Tab to update the description for Select Board.
  • Updated Figure: Block Diagram of the Hardware Setup.
  • Updated the hardware requirements in the Hardware and Software Requirements topics for all design examples.
2019.04.24 19.1 19.1
  • Changed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
2018.09.24 18.0 18.0
  • Updated Table: Parameters in the Example Design Tab to include a note to parameters Enable NPDME support and Analog Voltage to clarify that these options are only available from Intel Quartus Prime Pro Edition version 17.0 onwards.
  • Removed Debug Signals topic from the 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices chapter.
  • Updated the Configuration Registers Description chapter:
    • Added the following topics:
      • Register Access Definition
      • 1G/2.5G/5G/10G PHY
    • Removed the Register Map topic.
  • Added Timing Constraints topic to the following design example chapters:
    • 10M/100M/1G/2.5G/10G Ethernet Design for Intel Stratix 10 Devices
    • 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices
    • 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices
2018.08.08 18.0 18.0
  • Updated Table: Hardware Test Cases of the 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices chapter to update the description for source gen_conf.tcl command of the SFP+ loopback test case.
  • Updated Figure: Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example.
  • Updated Table: Avalon-MM Interface Signals:
    • Added the following signals:
      • csr_mch_write
      • csr_mch_writedata
      • csr_mch_read
      • csr_mch_readdata
      • csr_mch_address
      • csr_mch_waitrequest
    • Removed the following signals:
      • csr_write
      • csr_writedata
      • csr_read
      • csr_readdata
      • csr_address
      • csr_waitrequest
2018.05.16 18.0 18.0
  • Updated for latest branding standards.
  • Made editorial text updates throughout the document.
  • Added support for Xcelium simulator.
  • Renamed the document as Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IP Design Example User Guide.
  • Updated the procedure steps of the Compiling and Testing the Design in Hardware topic.
  • Updated the Test Cases topic of the 10BASE-R Ethernet Design Example for Intel Stratix 10 Devices chapter.
  • Updated the 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices chapter:
    • Updated all references to 10G USXGMII references to 10M/100M/1G/2.5G/5G/10G (USXGMII).
    • Added 1588v2 feature support to the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example chapter.
    • Added new Simulation topics:
      • Test Case—Design Example with the IEEE 1588v2 Feature
      • Test Case—Design Example without the IEEE 1588v2 Feature
    • Updated Table: Command Parameters.
    • Updated Table: Register Map to include byte offset for Native PHY Reconfiguration block.
  • Updated the Test Procedure topic of the 10M/100M/1G/2.5G Ethernet Design Example for Intel Stratix 10 Devices chapter.
  • Updated the Hardware and Software Requirements, Design Components, and Hardware Testing topics for all design example chapters.
  • Updated the following Tables:
    • Directory and File Description
    • Parameters in the Example Design Tab
    • Clock and Reset Interface Signals
  • Updated the following Figures:
    • Block Diagram—10GBASE-R Ethernet Design Example
    • Clocking and Reset Scheme for 10GBASE-R Design Example
    • Reset Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example
    • Block Diagram—1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
    • Block Diagram—1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
    • Reset Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
    • Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example Without IEEE 1588v2 Feature
    • Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
2018.03.28 17.1 17.1
  • Updated Figure: Clocking Scheme for 10G USXGMII Ethernet Design Example.
Date Version Changes
November 2017 2017.12.04
  • Updated Figure: Example Design Tab.
  • Added Hardware Testing, Test Cases, and Debug Signals topics for the 10BASE-R Ethernet Design Examplechapter.
  • Updated the description in the Hardware Testing topic for the following Ethernet design examples:
    • 10M/100M/1G/2.5G/10G
    • 1G/2.5G with IEEE 1588v2 Feature
    • 1G/2.5G/10G with IEEE 1588v2 Feature
    • 10G USXGMII
  • Added Changing to SFP+ Setting topic for 1G/2.5G/10G Ethernet design example with IEEE 1588v2 Feature chapter.
  • Made editorial text and structure update.
2017.11.06
  • Rebranded as Intel.
  • Renamed the document as Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Stratix 10 Devices.
  • Updated the Quick Start Guide section:
    • Updated the "Directory and File Description" table.
    • Removed rtl directory from the "Directory and File Description" table.
    • Changed heading title of the Design Parameters Description topic to Design Example Parameters.
    • Updated the "Parameters in the Example Design Tab" table:
      • Added Analog Voltage and Enable ADME support parameters and descriptions.
      • Updated the descriptions for Generate File Format and Select Board parameters.
    • Updated the Procedure subtopic under the Compiling and Simulating the Design topic.
    • Updated the Procedure subtopic under the Compiling and Testing the Design in Hardware topic.
  • Updated entire 1G/2.5G/10G Ethernet Design Example chapter to 10M/100M/1G/2.5G/10G Ethernet Design Example chapter.
  • Updated the 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices topic.
  • Added 10G USXGMII Ethernet Design Example chapter.
  • Added 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature chapter.
  • Updated the description in the "Features" topic for the 10GBASE-R, 10M/100M/1G/2.5G/10G, 1G/2.5G with IEEE 1588v2 Feature, 1G/2.5G, 1G/2.5G/10G with IEEE 1588v2 Feature, and 10G USXGMII Ethernet design examples.
  • Updated the "Design Component" table for the 10GBASE-R, 10M/100M/1G/2.5G/10G, 1G/2.5G with IEEE 1588v2 Feature, 1G/2.5G, 1G/2.5G/10G with IEEE 1588v2 Feature, and 10G USXGMII Ethernet design examples.
  • Updated the Hardware and Software Requirements topic for the 10GBASE-R, 10M/100M/1G/2.5G/10G, 1G/2.5G with IEEE 1588v2 Feature, 1G/2.5G, 1G/2.5G/10G with IEEE 1588v2 Feature, and 10G USXGMII Ethernet design examples.
  • Updated Figures:
    • Example Design Tab
    • Block Diagram of the Hardware Setup
    • Block Diagram—10GBASE-R Design Example
    • Clocking and Reset Scheme for 10GBASE-R Design Example
    • Clocking Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example
    • Reset Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example
    • Clocking Scheme for 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
    • Reset Scheme for 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
    • Interface Signals of the 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
    • Clocking Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
    • Reset Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
    • Interface Signals of the 1G/2.5G/10G Ethernet Design Examples with IEEE 1588v2 Feature
    • Clocking Scheme for 10G USXGMII Ethernet Design Example
    • Reset Scheme for 10G USXGMII Ethernet Design Example
    • Interface Signals of the 10G USXGMII Ethernet Design Example
  • Updated the "RX Configuration and Status Registers" table: Updated the HW Reset value for 0x2004 from 1518 to 0x5EE(1518).
  • Updated the Configuration Registers Description chapter:
    • Updated the PHY topic:
      • Removed the "PMA Registers", "PCS Registers", and "Stratix 10 GMII PCS Registers" tables.
      • Added Register Map and Register Definitions subtopics.
    • Merged the 10G TOD and 1G TOD topics with the Master TOD and changed heading title to ToD.
    • Updated "ToD Register Map" table: Added bits information.
  • Made text updates throughout the document.
May 2017 2017.05.08
  • Updated the Procedure topic in the Quick Start Guide chapter.
  • Added the Compiling and Testing the Design in Hardware topic in the Quick Start Guide chapter.
  • Updated the Software Requirements topic in the 10GBASE-R Design Example for Stratix 10 chapter.
  • Updated the Register Map table in the 10GBASE-R Design Example for Stratix 10 chapter.
  • Updated the Clocking and Reset Scheme for 10GBASE-R Design Example figure.
  • Added 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature chapter.
  • Added 1G/2.5G/10G Ethernet Design Example chapter.
  • Added Interface Signals Description for Stratix 10 chapter.
  • Added Configuration Registers Description for Stratix 10 chapter.
  • Updated the description for csr_clk signal in the Clock and Reset Interface Signals table.
  • Editorial fix to the Interface Signals and Configuration Registers topics for 10GBASE-R Design Example chapter.
  • Updated document part number from UG-20016-S10 to UG-20073.
October 2016 2016.10.31 Initial release.