Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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7.5. Status Interface

Table 23.  Status Interface Signals
Signal Direction Description

led_link

block_lock

rx_block_lock

Out Asserted when the link synchronization is successful.

led_an

ethernet_1g_an

Out Asserted when auto-negotiation is completed.

led_char_err

ethernet_1g_char_err

Out Asserted when a 10-bit character error is detected in the RX data.

led_disp_err

ethernet_1g_disp_err

Out Asserted when a 10-bit running disparity error is detected in the RX data.

channel_ready

channel_tx_ready

channel_rx_ready

tx_ready_export

rx_ready_export

Out Asserted when the channel is ready for data transmission.
atx_pll_locked Out Asserted when the TX PLL is locked.