Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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1.3.1.1. Updating PHY IP Design File Names

If you change the target device in the hardware design example and regenerate the IP component, the random string suffixes of the PHY IP component design file names may change.

To ensure proper simulation elaboration, follow these steps:

  1. Open the simulation script for the simulator of your choice.
    Simulator Simulator Script
    ModelSim* <Example Design>/simulation/ed_sim/setup_scripts/common/modelsim_files.tcl
    VCS* <Example Design>/simulation/ed_sim/setup_scripts/common/vcs_files.tcl

    <Example Design>/simulation/ed_sim/setup_scripts/common/vcsmx_files.tcl

    Xcelium* <Example Design>/simulation/ed_sim/setup_scripts/common/xcelium_files.tcl
  2. Edit the PHY IP design files names in the simulation script to match with the regenerated PHY IP component design file names.

    Examples of the PHY IP design files names with random string suffix that need to be updated:

    • alt_mgbaset_phy_altera_xcvr_native_s10_htile_1921_dsmw74y.sv
    • alt_xcvr_native_rcfg_opt_logic_dsmw74y.sv
    • alt_mgbaset_phy_alt_mge_phy_1930_3oqbkgq.v

    1921 and 1930 are IP versions. dsmw74y and 3oqbkgq are the random strings that specific to the Quartus version and transceiver tile type.

  3. Save the file.