Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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Document Table of Contents

1.3.2. Testbench

Figure 4. Block Diagram of the Testbench
Table 3.  Testbench Components
Component Description
Device under test (DUT) The design example.
Avalon® driver Consists of Avalon® streaming master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon® memory-mapped interface of the DUT.
Ethernet packet monitors Monitor TX and RX datapaths, and display the frames in the simulator console.