Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
Document Table of Contents

5.3.3. Reset Scheme

The global reset signal of the design example is asynchronous and active-low. Asserting this signal resets all channels and their components. Upon power-up, reset the design example.

Figure 29. Reset Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature