Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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3.3.1. Design Components

Table 7.  Design Components
Component Description
LL 10GbE MAC

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 10M/100M/1G/2.5G/10G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • TX and RX datapath Reset/Default To Enable: Selected
  • All Legacy Ethernet 10G MAC Interfaces options: Selected
PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP with the following configuration:
  • Speed: 1G/2.5G/10G
  • SGMII bridge: Selected
  • Connect to MGBASE-T PHY: Selected
  • Connect to NBASE-T PHY: Not selected
  • PHY ID (32 bit): 0x00000000
  • VCCR_GXB and VCC_GXB supply voltage for the Transceiver: 1_0V
  • Reference clock frequency for 10GbE (MHz): 644.53125
  • Selected TX PMA local clock division factor for 1 GbE: 1
  • Selected TX PMA local clock division factor for 2.5 GbE: 1
  • Enable Native PHY Debug Master Endpoint: Not selected
  • Enable capability registers: Not selected
  • Enable control and status registers: Not selected
  • Enable PRBS soft accumulators: Not selected
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel® FPGA IP. Resets the transceiver.
Address Decoder Decodes the addresses of the components.
Avalon® Memory-Mapped Mux Transceiver Reconfig Provides the transceiver reconfig block and system console access to the Avalon® memory-mapped interface of the PHY.
Transceiver Reconfig Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.
ATX PLL Generates a TX serial clock for the Intel® Stratix® 10 2.5G and 10G transceiver.
fPLL Generates a TX serial clock for the Intel® Stratix® 10 1G transceiver.