Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
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6.4.1. Test Case—Design Example with the IEEE 1588v2 Feature

The simulation test case performs the following steps:

  1. Starts up the design example with an operating speed of 10G.
  2. Configures the MAC, PHY, and FIFO buffer for both channels.
  3. Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for each channel.
  4. Sends the following packets:
    • Non-PTP
    • No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
    • VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP
    • Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
    • No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
    • VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
    • Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
  5. Repeats steps 2 to 4 for 10M, 100M, 1G, 2.5G, and 5G.

When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.

Figure 40. Sample Simulation Output