Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 1/11/2022
Document Table of Contents

3.3.4. Timing Constraints

When you configure the PHY in 1G/2.5G/10G (MGBASE-T) configuration, Intel® recommends that you refer to the Timing Constraints section of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide for details on the timing constraint examples.

In addition, you can set false path from native PHY 10G clock to Low Latency (LL) Ethernet 10G (10GbE) MAC logic and vice versa. Since the LL 10GbE MAC logic is not running 10G clock, you do not need to ensure timing closure for LL 10GbE MAC datapath at 10G clock. For example:
set_false_path -from [get_clocks \$profile2_clk] \\
                   -to   [get_registers *|alt_em10g32:*|*]
set_false_path -from [get_registers *|alt_em10g32:*|*] \\
                   -to   [get_clocks \$profile2_clk]
where the path indicated by profile2 is associated to the native PHY 10G clock whereas the alt_em10g32 path indicates the LL 10GbE MAC logic.