Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

16.4.4.1. STIG Operation

The Software Triggered Instruction Generator (STIG) is used to access the volatile and non-volatile configuration registers, the legacy SPI status register, and other status and protection registers. The STIG also is used to perform ERASE functions. The direct and indirect access controllers are used only to transfer data. The flashcmd register uses the following parameters to define the command to be issued to the flash device:

  • Instruction opcode
  • Number of address bytes
  • Number of dummy bytes
  • Number of write data bytes
  • Write data
  • Number of read data bytes

The address is specified through the flash command address register (flashcmdaddr). Once these settings have been specified, software can trigger the command with the execute command field (execcmd) of the flashcmd register and wait for its completion by polling the command execution status bit (cmdexecstat) of the flashcmd register. A maximum of eight data bytes may be read from the flash command read data lower (flashcmdrddatalo) and flash command read data upper (flashcmdrddataup) registers or written to the flash command write data lower (flashcmdwrdatalo) and flash command write data upper (flashcmdwrdataup) registers per command.

Commands issued through the STIG have a higher priority than all other read accesses and therefore interrupt any read commands being requested by the direct or indirect controllers. However, the STIG does not interrupt a write sequence that may have been issued through the direct or indirect access controller. In these cases, it might take a long time for the cmdexecstat bit of the flashcmd register indicates the operation is complete.

Note: Intel recommends using the STIG instead of the SPI legacy mode to access the flash device registers and perform erase operations.