Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

16.4.8.1. Write Request

The Write Enable Latch (WEL) bit within the flash device itself must be high before a write sequence can be issued. The command generator automatically issues the Write Enable (WREN) instruction to set the WEL bit before triggering a write command through the direct or indirect access controllers. When write requests are no longer received and all outstanding requests have been sent, then the flash device starts the page program write cycle. Any incoming request at this time is held in wait states until the cycle has completed. The controller automatically polls the flash device Read Status Register (RDSR) to identify when the write cycle has completed. This continues until the Write In Progress bit and WEL bit have cleared to zero. The op-code for the WREN instruction is typically 0x06h and 0x05h for the RDSR instruction.
Note: These op-codes are common between devices.