Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

27.2.3. PLL Reference Clocks

Table 220.  PLL Reference Clock Parameters

Parameter Name

Parameter Description

Clock Interface Name

Enable FPGA-to-HPS peripheral PLL reference clock

Enable the interface for FPGA fabric to supply reference clock to HPS peripheral PLL

f2h_periph_ref_clock

Enable FPGA-to-HPS SDRAM PLL reference clock

Enable the interface for FPGA fabric to supply reference clock to HPS SDRAM PLL

f2h_sdram_ref_clock