Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

16.4.8. Configuring the Flash Device

For read and write accesses, software must initialize the device read instruction register (devrd) and the device write instruction register (devwr). These registers include fields to initialize the instruction opcodes that should be used as well as the instruction type, and whether the instruction uses single, dual or quad pins for address and data transfer. To ensure the quad SPI controller can operate from a reset state, the opcode registers reset to opcodes compatible with single I/O flash devices.

The quad SPI flash controller uses the instruction transfer width field (instwidth) of the devrd register to set the instruction transfer width for both reads and writes. There is no instwidth field in the devwr register. If instruction type is set to dual or quad mode, the address transfer width (addrwidth) and data transfer width (datawidth) fields of both registers are redundant because the address and data type is based on the instruction type. Thus, software can support the less common flash instructions where the opcode, address, and data are sent on two or four lanes. For most instructions, the opcodes are sent serially to the flash device, even for dual and quad instructions. One of the flash devices that supports instructions that can send the opcode over two or four lanes is the Micron N25Q128. For reference, the Quad SPI Configuration for Micron N25Q128 Device (Read Instructions) and the Quad SPI Configuration for Micron N25Q128 Device (Write Instructions) tables show how software should configure the quad SPI controller for each specific read and write instruction, respectively, supported by the Micron N25Q128 device.

Table 160.  Quad SPI Configuration for Micron N25Q128 Device (Read Instructions)
Instruction Lanes Used By Opcode Lanes Used to Send Address Lanes Used to Send Data instwidth Value addrwidth Value datawidth Value
Read 1 1 1 0 0 0
Fast read 1 1 1 0 0 0
Dual output fast read (DOFR) 1 1 2 0 0 1
Dual I/O fast read (DIOFR) 1 2 2 0 1 1
Quad output fast read (QOFR) 1 1 4 0 0 2
Quad I/O fast read (QIOFR) 1 4 4 0 2 2
Dual command fast read (DCFR) 2 2 2 1 Don’t care Don’t care
Quad command fast read (QCFR) 4 4 4 2 Don’t care Don’t care
Table 161.  Quad SPI Configuration for Micron N25Q128 Device (Write Instructions)
Instruction Lanes Used By Opcode Lanes Used to Send Address Lanes Used to Send Data instwidth Value addrwidth Value datawidth Value
Page program 1 1 1 0 0 0
Dual input fast program (DIFP) 1 1 2 0 0 1
Dual input extended fast program (DIEFP) 1 2 2 0 1 1
Quad input fast program (QIFP) 1 1 4 0 0 2
Quad input extended fast program (QIEFP) 1 4 4 0 2 2
Dual command fast program (DCFP) 2 2 2 1 Don’t care Don’t care
Quad command fast program (QCFP) 4 4 4 2 Don’t care Don’t care