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Ixiasoft
1. Arria® V Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Clock Manager
4. Reset Manager
5. FPGA Manager
6. System Manager
7. Scan Manager
8. System Interconnect
9. HPS-FPGA Bridges
10. CoreSight* Debug and Trace
11. SDRAM Controller Subsystem
12. On-Chip Memory
13. NAND Flash Controller
14. SD/MMC Controller
15. Quad SPI Flash Controller
16. DMA Controller
17. Ethernet Media Access Controller
18. USB 2.0 OTG Controller
19. SPI Controller
20. I2C Controller
21. UART Controller
22. General-Purpose I/O Interface
23. Timer
24. Watchdog Timer
25. Introduction to the HPS Component
26. Instantiating the HPS Component
27. HPS Component Interfaces
28. Simulating the HPS Component
A. Booting and Configuration
8.3.1. Master to Slave Connectivity Matrix
8.3.2. System Interconnect Address Spaces
8.3.3. Master Caching and Buffering Overrides
8.3.4. Security
8.3.5. Configuring the Quality of Service Logic
8.3.6. Cyclic Dependency Avoidance Schemes
8.3.7. System Interconnect Master Properties
8.3.8. Interconnect Slave Properties
8.3.9. Upsizing Data Width Function
8.3.10. Downsizing Data Width Function
8.3.11. Lock Support
8.3.12. FIFO Buffers and Clock Crossing
8.3.13. System Interconnect Resets
10.1. Features of CoreSight* Debug and Trace
10.2. Arm* CoreSight* Documentation
10.3. CoreSight Debug and Trace Block Diagram and System Integration
10.4. Functional Description of CoreSight Debug and Trace
10.5. CoreSight* Debug and Trace Programming Model
10.6. CoreSight Debug and Trace Address Map and Register Definitions
10.4.1. Debug Access Port
10.4.2. System Trace Macrocell
10.4.3. Trace Funnel
10.4.4. CoreSight Trace Memory Controller
10.4.5. AMBA* Trace Bus Replicator
10.4.6. Trace Port Interface Unit
10.4.7. Embedded Cross Trigger System
10.4.8. Program Trace Macrocell
10.4.9. HPS Debug APB* Interface
10.4.10. FPGA Interface
10.4.11. Debug Clocks
10.4.12. Debug Resets
11.1. Features of the SDRAM Controller Subsystem
11.2. SDRAM Controller Subsystem Block Diagram
11.3. SDRAM Controller Memory Options
11.4. SDRAM Controller Subsystem Interfaces
11.5. Memory Controller Architecture
11.6. Functional Description of the SDRAM Controller Subsystem
11.7. SDRAM Power Management
11.8. DDR PHY
11.9. Clocks
11.10. Resets
11.11. Port Mappings
11.12. Initialization
11.13. SDRAM Controller Subsystem Programming Model
11.14. Debugging HPS SDRAM in the Preloader
11.15. SDRAM Controller Address Map and Register Definitions
13.1. NAND Flash Controller Features
13.2. NAND Flash Controller Block Diagram and System Integration
13.3. NAND Flash Controller Signal Descriptions
13.4. Functional Description of the NAND Flash Controller
13.5. NAND Flash Controller Programming Model
13.6. NAND Flash Controller Address Map and Register Definitions
14.1. Features of the SD/MMC Controller
14.2. SD/MMC Controller Block Diagram and System Integration
14.3. SD/MMC Controller Signal Description
14.4. Functional Description of the SD/MMC Controller
14.5. SD/MMC Controller Programming Model
14.6. SD/MMC Controller Address Map and Register Definitions
15.1. Features of the Quad SPI Flash Controller
15.2. Quad SPI Flash Controller Block Diagram and System Integration
15.3. Interface Signals
15.4. Functional Description of the Quad SPI Flash Controller
15.5. Quad SPI Flash Controller Programming Model
15.6. Quad SPI Flash Controller Address Map and Register Definitions
15.4.1. Overview
15.4.2. Data Slave Interface
15.4.3. SPI Legacy Mode
15.4.4. Register Slave Interface
15.4.5. Local Memory Buffer
15.4.6. DMA Peripheral Request Controller
15.4.7. Arbitration between Direct/Indirect Access Controller and STIG
15.4.8. Configuring the Flash Device
15.4.9. XIP Mode
15.4.10. Write Protection
15.4.11. Data Slave Sequential Access Detection
15.4.12. Clocks
15.4.13. Resets
15.4.14. Interrupts
17.6.1. System Level EMAC Configuration Registers
17.6.2. EMAC FPGA Interface Initialization
17.6.3. EMAC HPS Interface Initialization
17.6.4. DMA Initialization
17.6.5. EMAC Initialization and Configuration
17.6.6. Performing Normal Receive and Transmit Operation
17.6.7. Stopping and Starting Transmission
17.6.8. Programming Guidelines for Energy Efficient Ethernet
17.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
18.1. Features of the USB OTG Controller
18.2. USB OTG Controller Block Diagram and System Integration
18.3. USB 2.0 ULPI PHY Signal Description
18.4. Functional Description of the USB OTG Controller
18.5. USB OTG Controller Programming Model
18.6. USB 2.0 OTG Controller Address Map and Register Definitions
28.1. Simulation Flows
28.2. Clock and Reset Interfaces
28.3. FPGA-to-HPS AXI Slave Interface
28.4. HPS-to-FPGA AXI Master Interface
28.5. Lightweight HPS-to-FPGA AXI Master Interface
28.6. FPGA-to-HPS SDRAM Interface
28.7. HPS-to-FPGA MPU Event Interface
28.8. Interrupts Interface
28.9. HPS-to-FPGA Debug APB* Interface
28.10. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
28.11. HPS-to-FPGA Cross-Trigger Interface
28.12. HPS-to-FPGA Trace Port Interface
28.13. FPGA-to-HPS DMA Handshake Interface
28.14. Boot from FPGA Interface
28.15. General Purpose Input Interface