Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 7/08/2021
Public
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Document Table of Contents
Document Table of Contents
1. Arria® V Hard Processor System Technical Reference Manual Revision History 2. Introduction to the Hard Processor System 3. Clock Manager 4. Reset Manager 5. FPGA Manager 6. System Manager 7. Scan Manager 8. System Interconnect 9. HPS-FPGA Bridges 10. CoreSight* Debug and Trace 11. SDRAM Controller Subsystem 12. On-Chip Memory 13. NAND Flash Controller 14. SD/MMC Controller 15. Quad SPI Flash Controller 16. DMA Controller 17. Ethernet Media Access Controller 18. USB 2.0 OTG Controller 19. SPI Controller 20. I2C Controller 21. UART Controller 22. General-Purpose I/O Interface 23. Timer 24. Watchdog Timer 25. Introduction to the HPS Component 26. Instantiating the HPS Component 27. HPS Component Interfaces 28. Simulating the HPS Component A. Booting and Configuration
2. Introduction to the Hard Processor System
2.1. Features of the HPS 2.2. HPS Block Diagram and System Integration 2.3. Endian Support 2.4. Introduction to the Hard Processor System Address Map
2.2. HPS Block Diagram and System Integration
2.2.1. HPS Block Diagram 2.2.2. Cortex-A9 MPCore 2.2.3. HPS Interfaces 2.2.4. System Interconnect 2.2.5. On-Chip Memory 2.2.6. Flash Memory Controllers 2.2.7. Support Peripherals 2.2.8. Interface Peripherals 2.2.9. CoreSight Debug and Trace
2.2.3. HPS Interfaces
2.2.3.1. HPS–FPGA Memory-Mapped Interfaces 2.2.3.2. Other HPS Interfaces
2.2.4. System Interconnect
2.2.4.1. SDRAM Controller Subsystem
2.2.4.1. SDRAM Controller Subsystem
2.2.4.1.1. SDRAM Controller 2.2.4.1.2. DDR PHY
2.2.5. On-Chip Memory
2.2.5.1. On-Chip RAM 2.2.5.2. Boot ROM
2.2.6. Flash Memory Controllers
2.2.6.1. NAND Flash Controller 2.2.6.2. Quad SPI Flash Controller 2.2.6.3. SD/MMC Controller
2.2.7. Support Peripherals
2.2.7.1. Clock Manager 2.2.7.2. Reset Manager 2.2.7.3. System Manager 2.2.7.4. Scan Manager 2.2.7.5. Timers 2.2.7.6. Watchdog Timers 2.2.7.7. DMA Controller 2.2.7.8. FPGA Manager
2.2.8. Interface Peripherals
2.2.8.1. EMACs 2.2.8.2. USB Controllers 2.2.8.3. I2C Controllers 2.2.8.4. UARTs 2.2.8.5. SPI Master Controllers 2.2.8.6. SPI Slave Controllers 2.2.8.7. GPIO Interfaces
2.4. Introduction to the Hard Processor System Address Map
2.4.1. HPS Address Spaces 2.4.2. HPS Peripheral Region Address Map
2.4.1. HPS Address Spaces
2.4.1.1. SDRAM Address Space 2.4.1.2. MPU Address Space 2.4.1.3. L3 Address Space
3. Clock Manager
3.1. Features of the Clock Manager 3.2. Clock Manager Block Diagram and System Integration 3.3. Functional Description of the Clock Manager 3.4. Clock Manager Address Map and Register Definitions
3.2. Clock Manager Block Diagram and System Integration
3.2.1. L4 Peripheral Clocks
3.3. Functional Description of the Clock Manager
3.3.1. Clock Manager Building Blocks 3.3.2. Hardware-Managed and Software-Managed Clocks 3.3.3. Clock Groups 3.3.4. Resets 3.3.5. Safe Mode 3.3.6. Interrupts 3.3.7. Clock Usage By Module
3.3.1. Clock Manager Building Blocks
3.3.1.1. PLLs 3.3.1.2. FREF, FVCO, and FOUT Equations 3.3.1.3. Dividers 3.3.1.4. Clock Gating 3.3.1.5. Control and Status Registers
3.3.3. Clock Groups
3.3.3.1. OSC1 Clock Group 3.3.3.2. Main Clock Group 3.3.3.3. Peripheral Clock Group
3.3.3.2. Main Clock Group
3.3.3.2.1. Changing Values That Affect Main Clock Group PLL Lock
3.3.3.3. Peripheral Clock Group
3.3.3.3.1. Flash Controller Clocks 3.3.3.3.2. SDRAM Clock Group
3.3.4. Resets
3.3.4.1. Cold Reset 3.3.4.2. Warm Reset
4. Reset Manager
4.1. Reset Manager Block Diagram and System Integration 4.2. Functional Description of the Reset Manager 4.3. Reset Manager Address Map and Register Definitions
4.1. Reset Manager Block Diagram and System Integration
4.1.1. HPS External Reset Sources 4.1.2. Reset Controller 4.1.3. Module Reset Signals 4.1.4. Slave Interface and Status Register
4.1.3. Module Reset Signals
4.1.3.1. Modules Requiring Software Deassert
4.2. Functional Description of the Reset Manager
4.2.1. Reset Sequencing 4.2.2. Reset Pins 4.2.3. Reset Effects 4.2.4. Altering Warm Reset System Response 4.2.5. Reset Handshaking
4.2.1. Reset Sequencing
4.2.1.1. Cold Reset Assertion Sequence 4.2.1.2. Warm Reset Assertion Sequence 4.2.1.3. Cold and Warm Reset Deassertion Sequence
5. FPGA Manager
5.1. Features of the FPGA Manager 5.2. FPGA Manager Block Diagram and System Integration 5.3. Functional Description of the FPGA Manager 5.4. FPGA Manager Address Map and Register Definitions
5.3. Functional Description of the FPGA Manager
5.3.1. FPGA Manager Building Blocks 5.3.2. FPGA Configuration 5.3.3. FPGA Status 5.3.4. Error Message Extraction 5.3.5. Boot Handshake 5.3.6. General Purpose I/O 5.3.7. Clock 5.3.8. Reset
5.3.1. FPGA Manager Building Blocks
5.3.1.1. Fabric I/O 5.3.1.2. Monitor
5.3.2. FPGA Configuration
5.3.2.1. Power Up Phase 5.3.2.2. Reset Phase 5.3.2.3. Configuration Phase 5.3.2.4. Initialization Phase 5.3.2.5. User Mode
6. System Manager
6.1. Features of the System Manager 6.2. System Manager Block Diagram and System Integration 6.3. Functional Description of the System Manager 6.4. System Manager Address Map and Register Definitions
6.3. Functional Description of the System Manager
6.3.1. Boot Configuration and System Information 6.3.2. Additional Module Control 6.3.3. Boot ROM Code 6.3.4. FPGA Interface Enables 6.3.5. ECC and Parity Control 6.3.6. Preloader Handoff Information 6.3.7. Clocks 6.3.8. Resets
6.3.2. Additional Module Control
6.3.2.1. DMA Controller 6.3.2.2. NAND Flash Controller 6.3.2.3. EMAC 6.3.2.4. USB 2.0 OTG Controller 6.3.2.5. SD/MMC Controller 6.3.2.6. Watchdog Timer
6.3.3. Boot ROM Code
6.3.3.1. L3 Interconnect
7. Scan Manager
7.1. Features of the Scan Manager 7.2. Scan Manager Block Diagram and System Integration 7.3. Functional Description of the Scan Manager 7.4. Scan Manager Address Map and Register Definitions
7.2. Scan Manager Block Diagram and System Integration
7.2.1. Arm* JTAG-AP Signal Use in the Scan Manager 7.2.2. Arm* JTAG-AP Scan Chains
7.3. Functional Description of the Scan Manager
7.3.1. Configuring HPS I/O Scan Chains 7.3.2. Communicating with the JTAG TAP Controller 7.3.3. JTAG-AP FIFO Buffer Access and Byte Command Protocol 7.3.4. Clocks 7.3.5. Resets
7.4. Scan Manager Address Map and Register Definitions
7.4.1. JTAG-AP Register Name Cross Reference Table
8. System Interconnect
8.1. Features of the System Interconnect 8.2. System Interconnect Block Diagram and System Integration 8.3. Functional Description of the Interconnect 8.4. System Interconnect Address Map and Register Definitions
8.2. System Interconnect Block Diagram and System Integration
8.2.1. Interconnect Block Diagram 8.2.2. System Interconnect Architecture 8.2.3. Main Connectivity Matrix
8.3. Functional Description of the Interconnect
8.3.1. Master to Slave Connectivity Matrix 8.3.2. System Interconnect Address Spaces 8.3.3. Master Caching and Buffering Overrides 8.3.4. Security 8.3.5. Configuring the Quality of Service Logic 8.3.6. Cyclic Dependency Avoidance Schemes 8.3.7. System Interconnect Master Properties 8.3.8. Interconnect Slave Properties 8.3.9. Upsizing Data Width Function 8.3.10. Downsizing Data Width Function 8.3.11. Lock Support 8.3.12. FIFO Buffers and Clock Crossing 8.3.13. System Interconnect Resets
8.3.2. System Interconnect Address Spaces
8.3.2.1. Available Address Maps 8.3.2.2. L3 Address Space 8.3.2.3. MPU Address Space 8.3.2.4. SDRAM Address Space 8.3.2.5. Address Remapping
8.3.2.5. Address Remapping
8.3.2.5.1. Bit Fields for Modifying the Memory Map
8.3.4. Security
8.3.4.1. Slave Security 8.3.4.2. Master Security
8.3.6. Cyclic Dependency Avoidance Schemes
8.3.6.1. Single Slave 8.3.6.2. Single Slave Per ID 8.3.6.3. Single Active Slave
8.3.9. Upsizing Data Width Function
8.3.9.1. Incrementing Bursts 8.3.9.2. Wrapping Bursts 8.3.9.3. Fixed Bursts 8.3.9.4. Bypass Merge
8.3.10. Downsizing Data Width Function
8.3.10.1. Incrementing Bursts 8.3.10.2. Wrapping Bursts 8.3.10.3. Fixed Bursts 8.3.10.4. Bypass Merge
8.3.12. FIFO Buffers and Clock Crossing
8.3.12.1. Data Release Mechanism
9. HPS-FPGA Bridges
9.1. Features of the HPS-FPGA Bridges 9.2. HPS-FPGA Bridges Block Diagram and System Integration 9.3. Functional Description of the HPS-FPGA Bridges 9.4. HPS-FPGA Bridges Address Map and Register Definitions
9.3. Functional Description of the HPS-FPGA Bridges
9.3.1. The Global Programmers View 9.3.2. Functional Description of the FPGA-to-HPS Bridge 9.3.3. Functional Description of the HPS-to-FPGA Bridge 9.3.4. Functional Description of the Lightweight HPS-to-FPGA Bridge 9.3.5. Clocks and Resets 9.3.6. Data Width Sizing
9.3.2. Functional Description of the FPGA-to-HPS Bridge
9.3.2.1. FPGA-to-HPS Access to ACP 9.3.2.2. FPGA-to-HPS Bridge Slave Signals
9.3.3. Functional Description of the HPS-to-FPGA Bridge
9.3.3.1. HPS-to-FPGA Bridge Master Signals
9.3.4. Functional Description of the Lightweight HPS-to-FPGA Bridge
9.3.4.1. Lightweight HPS-to-FPGA Bridge Master Signals
9.3.5. Clocks and Resets
9.3.5.1. FPGA-to-HPS Bridge Clocks and Resets 9.3.5.2. HPS-to-FPGA Bridge Clocks and Resets 9.3.5.3. Lightweight HPS-to-FPGA Bridge Clocks and Resets 9.3.5.4. Taking HPS-FPGA Bridges Out of Reset 9.3.5.5. GPV Clocks
10. CoreSight* Debug and Trace
10.1. Features of CoreSight* Debug and Trace 10.2. Arm* CoreSight* Documentation 10.3. CoreSight Debug and Trace Block Diagram and System Integration 10.4. Functional Description of CoreSight Debug and Trace 10.5. CoreSight* Debug and Trace Programming Model 10.6. CoreSight Debug and Trace Address Map and Register Definitions
10.4. Functional Description of CoreSight Debug and Trace
10.4.1. Debug Access Port 10.4.2. System Trace Macrocell 10.4.3. Trace Funnel 10.4.4. CoreSight Trace Memory Controller 10.4.5. AMBA* Trace Bus Replicator 10.4.6. Trace Port Interface Unit 10.4.7. Embedded Cross Trigger System 10.4.8. Program Trace Macrocell 10.4.9. HPS Debug APB* Interface 10.4.10. FPGA Interface 10.4.11. Debug Clocks 10.4.12. Debug Resets
10.4.4. CoreSight Trace Memory Controller
10.4.4.1. Embedded Trace FIFO 10.4.4.2. Embedded Trace Router
10.4.7. Embedded Cross Trigger System
10.4.7.1. Cross Trigger Interface 10.4.7.2. Cross Trigger Matrix
10.4.10. FPGA Interface
10.4.10.1. DAP 10.4.10.2. STM 10.4.10.3. FPGA-CTI 10.4.10.4. TPIU
10.5. CoreSight* Debug and Trace Programming Model
10.5.1. Coresight Component Address 10.5.2. STM Channels 10.5.3. CTI Trigger Connections to Outside the Debug System 10.5.4. Configuring Embedded Cross-Trigger Connections
10.5.3. CTI Trigger Connections to Outside the Debug System
10.5.3.1. csCTI 10.5.3.2. FPGA-CTI
10.5.4. Configuring Embedded Cross-Trigger Connections
10.5.4.1. Configuring Trigger Input 0 10.5.4.2. Triggering a Flush of Trace Data to the TPIU 10.5.4.3. Triggering an STM message 10.5.4.4. Triggering a Breakpoint on CPU 1
11. SDRAM Controller Subsystem
11.1. Features of the SDRAM Controller Subsystem 11.2. SDRAM Controller Subsystem Block Diagram 11.3. SDRAM Controller Memory Options 11.4. SDRAM Controller Subsystem Interfaces 11.5. Memory Controller Architecture 11.6. Functional Description of the SDRAM Controller Subsystem 11.7. SDRAM Power Management 11.8. DDR PHY 11.9. Clocks 11.10. Resets 11.11. Port Mappings 11.12. Initialization 11.13. SDRAM Controller Subsystem Programming Model 11.14. Debugging HPS SDRAM in the Preloader 11.15. SDRAM Controller Address Map and Register Definitions
11.4. SDRAM Controller Subsystem Interfaces
11.4.1. MPU Subsystem Interface 11.4.2. L3 Interconnect Interface 11.4.3. CSR Interface 11.4.4. FPGA-to-HPS SDRAM Interface
11.5. Memory Controller Architecture
11.5.1. Multi-Port Front End 11.5.2. Single-Port Controller
11.5.2. Single-Port Controller
11.5.2.1. Command Generator 11.5.2.2. Timer Bank Pool 11.5.2.3. Arbiter 11.5.2.4. Rank Timer 11.5.2.5. Write Data Buffer 11.5.2.6. ECC Block 11.5.2.7. AFI Interface 11.5.2.8. CSR Interface
11.6. Functional Description of the SDRAM Controller Subsystem
11.6.1. MPFE Operation Ordering 11.6.2. MPFE Multi-Port Arbitration 11.6.3. MPFE SDRAM Burst Scheduling 11.6.4. Single-Port Controller Operation
11.6.4. Single-Port Controller Operation
11.6.4.1. Command and Data Reordering 11.6.4.2. Bank Policy 11.6.4.3. Write Combining 11.6.4.4. Burst Length Support 11.6.4.5. ECC 11.6.4.6. Interleaving Options 11.6.4.7. AXI-Exclusive Support 11.6.4.8. Memory Protection 11.6.4.9. Example of Configuration for TrustZone
11.6.4.5. ECC
11.6.4.5.1. Byte Writes 11.6.4.5.2. ECC Write Backs 11.6.4.5.3. User Notification of ECC Errors
11.8. DDR PHY
11.8.1. DDR Calibration
11.10. Resets
11.10.1. Taking the SDRAM Controller Subsystem Out of Reset
11.12. Initialization
11.12.1. FPGA-to-SDRAM Protocol Details
11.12.1. FPGA-to-SDRAM Protocol Details
11.12.1.1. Avalon-MM Bidirectional Port 11.12.1.2. Avalon-MM Write-Only Port 11.12.1.3. Avalon-MM Read Port 11.12.1.4. AXI Port
11.13. SDRAM Controller Subsystem Programming Model
11.13.1. HPS Memory Interface Architecture 11.13.2. HPS Memory Interface Configuration 11.13.3. HPS Memory Interface Simulation 11.13.4. Generating a Preloader Image for HPS with EMIF
11.13.4. Generating a Preloader Image for HPS with EMIF
11.13.4.1. Creating a Project in Platform Designer (Standard) 11.13.4.2. Creating a Top-Level File and Adding Constraints
11.14. Debugging HPS SDRAM in the Preloader
11.14.1. Enabling UART or Semihosting Printout 11.14.2. Enabling Simple Memory Test 11.14.3. Enabling the Debug Report 11.14.4. Writing a Predefined Data Pattern to SDRAM in the Preloader
11.14.3. Enabling the Debug Report
11.14.3.1. Analysis of Debug Report
12. On-Chip Memory
12.1. On-Chip RAM 12.2. Boot ROM 12.3. On-Chip Memory Address Map and Register Definitions
12.1. On-Chip RAM
12.1.1. Features of the On-Chip RAM 12.1.2. On-Chip RAM Block Diagram and System Integration 12.1.3. Functional Description of the On-Chip RAM
12.1.3. Functional Description of the On-Chip RAM
12.1.3.1. On-Chip RAM Clocks 12.1.3.2. On-Chip RAM Resets 12.1.3.3. On-Chip RAM Initialization
12.2. Boot ROM
12.2.1. Features of the Boot ROM 12.2.2. Boot ROM Block Diagram and System Integration 12.2.3. Functional Description of the Boot ROM
12.2.3. Functional Description of the Boot ROM
12.2.3.1. Boot ROM Clocks 12.2.3.2. Boot ROM Resets
13. NAND Flash Controller
13.1. NAND Flash Controller Features 13.2. NAND Flash Controller Block Diagram and System Integration 13.3. NAND Flash Controller Signal Descriptions 13.4. Functional Description of the NAND Flash Controller 13.5. NAND Flash Controller Programming Model 13.6. NAND Flash Controller Address Map and Register Definitions
13.4. Functional Description of the NAND Flash Controller
13.4.1. Discovery and Initialization 13.4.2. Bootstrap Interface 13.4.3. Configuration by Host 13.4.4. Local Memory Buffer 13.4.5. Clocks 13.4.6. Resets 13.4.7. Indexed Addressing 13.4.8. Command Mapping 13.4.9. Data DMA 13.4.10. ECC
13.4.2. Bootstrap Interface
13.4.2.1. Bootstrap Setting Bits
13.4.3. Configuration by Host
13.4.3.1. Recommended Bootstrap Settings for 512-Byte Page Device 13.4.3.2. NAND Page Main and Spare Areas
13.4.5. Clocks
13.4.5.1. Clock Generation 13.4.5.2. Clock Enable 13.4.5.3. Clock Switching
13.4.6. Resets
13.4.6.1. Taking the NAND Flash Controller Out of Reset
13.4.7. Indexed Addressing
13.4.7.1. Register Map for Indexed Addressing 13.4.7.2. Indexed Addressing Host Usage
13.4.8. Command Mapping
13.4.8.1. MAP00 Commands 13.4.8.2. MAP01 Commands 13.4.8.3. MAP10 Commands 13.4.8.4. MAP11 Commands
13.4.8.1. MAP00 Commands
13.4.8.1.1. MAP00 Command Format 13.4.8.1.2. MAP00 Usage Limitations
13.4.8.2. MAP01 Commands
13.4.8.2.1. MAP01 Command Format 13.4.8.2.2. MAP01 Usage Limitations
13.4.8.3. MAP10 Commands
13.4.8.3.1. MAP10 Command Format 13.4.8.3.2. MAP10 Operations 13.4.8.3.3. MAP10 Usage Limitations
13.4.8.4. MAP11 Commands
13.4.8.4.1. MAP11 Control Format 13.4.8.4.2. MAP11 Usage Limitations
13.4.9. Data DMA
13.4.9.1. Multi-Transaction DMA Command 13.4.9.2. Burst DMA Command
13.4.9.1. Multi-Transaction DMA Command
13.4.9.1.1. Command-Data Pair Formats 13.4.9.1.2. Using Multi-Transaction DMA Commands
13.4.10. ECC
13.4.10.1. Correction Capability, Sector Size, and Check Bit Size 13.4.10.2. ECC Programming Modes 13.4.10.3. Preserving Bad Block Markers 13.4.10.4. Error Correction Status
13.4.10.2. ECC Programming Modes
13.4.10.2.1. Main Area Transfer Mode 13.4.10.2.2. Spare Area Transfer Mode 13.4.10.2.3. Main+Spare Area Transfer Mode
14. SD/MMC Controller
14.1. Features of the SD/MMC Controller 14.2. SD/MMC Controller Block Diagram and System Integration 14.3. SD/MMC Controller Signal Description 14.4. Functional Description of the SD/MMC Controller 14.5. SD/MMC Controller Programming Model 14.6. SD/MMC Controller Address Map and Register Definitions
14.1. Features of the SD/MMC Controller
14.1.1. SD Card Support Matrix 14.1.2. MMC Support Matrix
15. Quad SPI Flash Controller
15.1. Features of the Quad SPI Flash Controller 15.2. Quad SPI Flash Controller Block Diagram and System Integration 15.3. Interface Signals 15.4. Functional Description of the Quad SPI Flash Controller 15.5. Quad SPI Flash Controller Programming Model 15.6. Quad SPI Flash Controller Address Map and Register Definitions
15.4. Functional Description of the Quad SPI Flash Controller
15.4.1. Overview 15.4.2. Data Slave Interface 15.4.3. SPI Legacy Mode 15.4.4. Register Slave Interface 15.4.5. Local Memory Buffer 15.4.6. DMA Peripheral Request Controller 15.4.7. Arbitration between Direct/Indirect Access Controller and STIG 15.4.8. Configuring the Flash Device 15.4.9. XIP Mode 15.4.10. Write Protection 15.4.11. Data Slave Sequential Access Detection 15.4.12. Clocks 15.4.13. Resets 15.4.14. Interrupts
15.4.2. Data Slave Interface
15.4.2.1. Direct Access Mode 15.4.2.2. Indirect Access Mode
15.4.2.1. Direct Access Mode
15.4.2.1.1. Data Slave Remapping Example 15.4.2.1.2. AHB*
15.4.2.2. Indirect Access Mode
15.4.2.2.1. Indirect Read Operation 15.4.2.2.2. Indirect Write Operation 15.4.2.2.3. Consecutive Reads and Writes
15.4.4. Register Slave Interface
15.4.4.1. STIG Operation
15.4.8. Configuring the Flash Device
15.4.8.1. Write Request
15.4.13. Resets
15.4.13.1. Taking the Quad SPI Flash Controller Out of Reset 15.4.13.2. SRAM Initialization Procedure with ECC Enabled
15.5. Quad SPI Flash Controller Programming Model
15.5.1. Setting Up the Quad SPI Flash Controller 15.5.2. Indirect Read Operation with DMA Disabled 15.5.3. Indirect Read Operation with DMA Enabled 15.5.4. Indirect Write Operation with DMA Disabled 15.5.5. Indirect Write Operation with DMA Enabled 15.5.6. XIP Mode Operations
15.5.6. XIP Mode Operations
15.5.6.1. Entering XIP Mode 15.5.6.2. Exiting XIP Mode 15.5.6.3. XIP Mode at Power on Reset
15.5.6.1. Entering XIP Mode
15.5.6.1.1. Micron Quad SPI Flash Devices with Support for Basic-XIP 15.5.6.1.2. Micron Quad SPI Flash Devices without Support for Basic-XIP 15.5.6.1.3. Winbond Quad SPI Flash Devices 15.5.6.1.4. Spansion Quad SPI Flash Devices
16. DMA Controller
16.1. Features of the DMA Controller 16.2. DMA Controller Block Diagram and System Integration 16.3. Functional Description of the DMA Controller 16.4. DMA Controller Address Map and Register Definitions
16.3. Functional Description of the DMA Controller
16.3.1. Peripheral Request Interface
16.3.1. Peripheral Request Interface
16.3.1.1. Peripheral Request Interface Mapping
16.4. DMA Controller Address Map and Register Definitions
16.4.1. Address Map and Register Definitions
17. Ethernet Media Access Controller
17.1. Features of the Ethernet MAC 17.2. EMAC Block Diagram and System Integration 17.3. EMAC Signal Description 17.4. EMAC Internal Interfaces 17.5. Functional Description of the EMAC 17.6. Ethernet MAC Programming Model 17.7. Ethernet MAC Address Map and Register Definitions
17.1. Features of the Ethernet MAC
17.1.1. MAC 17.1.2. DMA 17.1.3. Management Interface 17.1.4. Acceleration 17.1.5. PHY Interface
17.3. EMAC Signal Description
17.3.1. HPS EMAC I/O Signals 17.3.2. FPGA EMAC I/O Signals 17.3.3. PHY Management Interface
17.3.3. PHY Management Interface
17.3.3.1. MDIO Interface 17.3.3.2. I2C External PHY Management Interface
17.4. EMAC Internal Interfaces
17.4.1. DMA Master Interface 17.4.2. Timestamp Interface
17.6. Ethernet MAC Programming Model
17.6.1. System Level EMAC Configuration Registers 17.6.2. EMAC FPGA Interface Initialization 17.6.3. EMAC HPS Interface Initialization 17.6.4. DMA Initialization 17.6.5. EMAC Initialization and Configuration 17.6.6. Performing Normal Receive and Transmit Operation 17.6.7. Stopping and Starting Transmission 17.6.8. Programming Guidelines for Energy Efficient Ethernet 17.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
17.6.8. Programming Guidelines for Energy Efficient Ethernet
17.6.8.1. Entering and Exiting the TX LPI Mode 17.6.8.2. Gating Off the CSR Clock in the LPI Mode
17.6.8.2. Gating Off the CSR Clock in the LPI Mode
17.6.8.2.1. Gating Off the CSR Clock in the RX LPI Mode 17.6.8.2.2. Gating Off the CSR Clock in the TX LPI Mode
17.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
17.6.9.1. Generating a Single Pulse on PPS 17.6.9.2. Generating a Pulse Train on PPS 17.6.9.3. Generating an Interrupt without Affecting the PPS
18. USB 2.0 OTG Controller
18.1. Features of the USB OTG Controller 18.2. USB OTG Controller Block Diagram and System Integration 18.3. USB 2.0 ULPI PHY Signal Description 18.4. Functional Description of the USB OTG Controller 18.5. USB OTG Controller Programming Model 18.6. USB 2.0 OTG Controller Address Map and Register Definitions
18.1. Features of the USB OTG Controller
18.1.1. Supported PHYS
18.4. Functional Description of the USB OTG Controller
18.4.1. USB OTG Controller Block Description 18.4.2. Local Memory Buffer 18.4.3. Clocks 18.4.4. Resets 18.4.5. Interrupts
18.4.1. USB OTG Controller Block Description
18.4.1.1. Master Interface 18.4.1.2. Slave Interface 18.4.1.3. Application Interface Unit 18.4.1.4. Packet FIFO Controller 18.4.1.5. SPRAM 18.4.1.6. MAC 18.4.1.7. Wakeup and Power Control 18.4.1.8. PHY Interface Unit 18.4.1.9. DMA
18.4.1.2. Slave Interface
18.4.1.2.1. Slave Interface CSR Unit
18.4.1.6. MAC
18.4.1.6.1. USB Transactions 18.4.1.6.2. Host Protocol 18.4.1.6.3. Device Protocol 18.4.1.6.4. OTG Protocol
18.4.4. Resets
18.4.4.1. Reset Requirements 18.4.4.2. Hardware Reset 18.4.4.3. Software Reset 18.4.4.4. Taking the USB 2.0 OTG Controller Out of Reset
18.5. USB OTG Controller Programming Model
18.5.1. Enabling ECC 18.5.2. Enabling SPRAM ECCs 18.5.3. Host Operation 18.5.4. Device Operation
18.5.3. Host Operation
18.5.3.1. Host Initialization 18.5.3.2. Host Transaction
18.5.4. Device Operation
18.5.4.1. Device Initialization 18.5.4.2. Device Transaction
18.5.4.2. Device Transaction
18.5.4.2.1. IN Transactions 18.5.4.2.2. OUT Transactions 18.5.4.2.3. Control Transfers
18.6. USB 2.0 OTG Controller Address Map and Register Definitions
18.6.1. USB OTG Controller Module Registers Address Map
18.6.1. USB OTG Controller Module Registers Address Map
18.6.1.1. USB Data FIFO Address Map 18.6.1.2. USB Direct Access FIFO RAM Address Map
19. SPI Controller
19.1. Features of the SPI Controller 19.2. SPI Block Diagram and System Integration 19.3. SPI Controller Signal Description 19.4. Functional Description of the SPI Controller 19.5. SPI Programming Model 19.6. SPI Controller Address Map and Register Definitions
19.2. SPI Block Diagram and System Integration
19.2.1. SPI Block Diagram
19.3. SPI Controller Signal Description
19.3.1. Interface to HPS I/O 19.3.2. FPGA Routing
19.4. Functional Description of the SPI Controller
19.4.1. Protocol Details and Standards Compliance 19.4.2. SPI Controller Overview 19.4.3. Transfer Modes 19.4.4. SPI Master 19.4.5. SPI Slave 19.4.6. Partner Connection Interfaces 19.4.7. DMA Controller Interface 19.4.8. Slave Interface 19.4.9. Clocks and Resets
19.4.2. SPI Controller Overview
19.4.2.1. Serial Bit-Rate Clocks 19.4.2.2. Transmit and Receive FIFO Buffers 19.4.2.3. SPI Interrupts
19.4.2.1. Serial Bit-Rate Clocks
19.4.2.1.1. SPI Master Bit-Rate Clock 19.4.2.1.2. SPI Slave Bit-Rate Clock
19.4.3. Transfer Modes
19.4.3.1. Transmit and Receive 19.4.3.2. Transmit Only 19.4.3.3. Receive Only 19.4.3.4. EEPROM Read
19.4.4. SPI Master
19.4.4.1. RXD Sample Delay 19.4.4.2. Data Transfers 19.4.4.3. Master SPI and SSP Serial Transfers 19.4.4.4. Master Microwire Serial Transfers
19.4.5. SPI Slave
19.4.5.1. Slave SPI and SSP Serial Transfers  19.4.5.2. Serial Transfers 19.4.5.3. Glue Logic for Master Port ss_in_n
19.4.6. Partner Connection Interfaces
19.4.6.1. Motorola SPI Protocol 19.4.6.2. Texas Instruments Synchronous Serial Protocol (SSP) 19.4.6.3. National Semiconductor Microwire Protocol
19.4.8. Slave Interface
19.4.8.1. Control and Status Register Access 19.4.8.2. Data Register Access
19.4.9. Clocks and Resets
19.4.9.1. Taking the SPI Controller Out of Reset
19.5. SPI Programming Model
19.5.1. Master SPI and SSP Serial Transfers 19.5.2. Master Microwire Serial Transfers 19.5.3. Slave SPI and SSP Serial Transfers 19.5.4. Slave Microwire Serial Transfers 19.5.5. Software Control for Slave Selection 19.5.6. DMA Controller Operation
19.5.5. Software Control for Slave Selection
19.5.5.1. Example: Slave Selection Software Flow for SPI Master 19.5.5.2. Example: Slave Selection Software Flow for SPI Slave
19.5.6. DMA Controller Operation
19.5.6.1. Transmit FIFO Buffer Underflow 19.5.6.2. Transmit FIFO Watermark 19.5.6.3. Transmit FIFO Buffer Overflow 19.5.6.4. Receive FIFO Buffer Overflow 19.5.6.5. Choosing Receive Watermark Level 19.5.6.6. Receive FIFO Buffer Underflow
19.5.6.2. Transmit FIFO Watermark
19.5.6.2.1. Example 1: Transmit FIFO Watermark Level = 64 19.5.6.2.2. Example 2: Transmit FIFO Watermark Level = 192
20. I2C Controller
20.1. Features of the I2C Controller 20.2. I2C Controller Block Diagram and System Integration 20.3. I2C Controller Signal Description 20.4. Functional Description of the I2C Controller 20.5. I2C Controller Programming Model 20.6. I2C Controller Address Map and Register Definitions
20.4. Functional Description of the I2C Controller
20.4.1. Feature Usage 20.4.2. Behavior 20.4.3. Protocol Details 20.4.4. Multiple Master Arbitration 20.4.5. Clock Frequency Configuration 20.4.6. SDA Hold Time 20.4.7. DMA Controller Interface 20.4.8. Clocks 20.4.9. Resets
20.4.2. Behavior
20.4.2.1. START and STOP Generation 20.4.2.2. Combined Formats
20.4.3. Protocol Details
20.4.3.1. START and STOP Conditions 20.4.3.2. Addressing Slave Protocol 20.4.3.3. Transmitting and Receiving Protocol 20.4.3.4. START BYTE Transfer Protocol
20.4.3.2. Addressing Slave Protocol
20.4.3.2.1. 7-Bit Address Format 20.4.3.2.2. 10-Bit Address Format
20.4.3.3. Transmitting and Receiving Protocol
20.4.3.3.1. Master-Transmitter and Slave-Receiver 20.4.3.3.2. Master-Receiver and Slave-Transmitter
20.4.4. Multiple Master Arbitration
20.4.4.1. Clock Synchronization
20.4.5. Clock Frequency Configuration
20.4.5.1. Minimum High and Low Counts
20.4.5.1. Minimum High and Low Counts
20.4.5.1.1. Calculating High and Low Counts
20.4.9. Resets
20.4.9.1. Taking the I2C Controller Out of Reset
20.5. I2C Controller Programming Model
20.5.1. Slave Mode Operation 20.5.2. Master Mode Operation 20.5.3. Disabling the I2C Controller 20.5.4. DMA Controller Operation
20.5.1. Slave Mode Operation
20.5.1.1. Initial Configuration 20.5.1.2. Slave-Transmitter Operation for a Single Byte 20.5.1.3. Slave-Receiver Operation for a Single Byte 20.5.1.4. Slave-Transfer Operation for Bulk Transfers
20.5.2. Master Mode Operation
20.5.2.1. Initial Configuration 20.5.2.2. Dynamic IC_TAR or IC_10BITADDR_MASTER Update 20.5.2.3. Master Transmit and Master Receive
20.5.4. DMA Controller Operation
20.5.4.1. Transmit FIFO Underflow 20.5.4.2. Transmit Watermark Level 20.5.4.3. Transmit FIFO Overflow 20.5.4.4. Receive FIFO Overflow 20.5.4.5. Receive Watermark Level 20.5.4.6. Receive FIFO Underflow
21. UART Controller
21.1. UART Controller Features 21.2. UART Controller Block Diagram and System Integration 21.3. UART Controller Signal Description 21.4. Functional Description of the UART Controller 21.5. DMA Controller Operation 21.6. UART Controller Address Map and Register Definitions
21.3. UART Controller Signal Description
21.3.1. HPS I/O Pins 21.3.2. FPGA Routing
21.4. Functional Description of the UART Controller
21.4.1. FIFO Buffer Support 21.4.2. UART(RS232) Serial Protocol 21.4.3. Automatic Flow Control 21.4.4. Clocks 21.4.5. Resets 21.4.6. Interrupts
21.4.3. Automatic Flow Control
21.4.3.1. Automatic RTS mode 21.4.3.2. Automatic CTS mode
21.4.5. Resets
21.4.5.1. Taking the UART Controller Out of Reset
21.4.6. Interrupts
21.4.6.1. Programmable THRE Interrupt
21.5. DMA Controller Operation
21.5.1. Transmit FIFO Underflow 21.5.2. Transmit Watermark Level 21.5.3. Transmit FIFO Overflow 21.5.4. Receive FIFO Overflow 21.5.5. Receive Watermark Level 21.5.6. Receive FIFO Underflow
21.5.2. Transmit Watermark Level
21.5.2.1. IIR_FCR.TET = 1 21.5.2.2. IIR_FCR.TET = 3
22. General-Purpose I/O Interface
22.1. Features of the GPIO Interface 22.2. GPIO Interface Block Diagram and System Integration 22.3. Functional Description of the GPIO Interface 22.4. GPIO Interface Programming Model 22.5. General-Purpose I/O Interface Address Map and Register Definitions
22.3. Functional Description of the GPIO Interface
22.3.1. Debounce Operation 22.3.2. Pin Directions 22.3.3. Taking the GPIO Interface Out of Reset 22.3.4. GPIO Pin State During Reset
23. Timer
23.1. Features of the Timer 23.2. Timer Block Diagram and System Integration 23.3. Functional Description of the Timer 23.4. Timer Programming Model 23.5. Timer Address Map and Register Definitions
23.3. Functional Description of the Timer
23.3.1. Clocks 23.3.2. Resets 23.3.3. Interrupts 23.3.4. FPGA Interface
23.4. Timer Programming Model
23.4.1. Initialization 23.4.2. Enabling the Timer 23.4.3. Disabling the Timer 23.4.4. Loading the Timer Countdown Value 23.4.5. Servicing Interrupts
23.4.5. Servicing Interrupts
23.4.5.1. Clearing the Interrupt 23.4.5.2. Checking the Interrupt Status 23.4.5.3. Masking the Interrupt
24. Watchdog Timer
24.1. Features of the Watchdog Timer 24.2. Watchdog Timer Block Diagram and System Integration 24.3. Functional Description of the Watchdog Timer 24.4. Watchdog Timer Programming Model 24.5. Watchdog Timer Address Map and Register Definitions
24.3. Functional Description of the Watchdog Timer
24.3.1. Watchdog Timer Counter 24.3.2. Watchdog Timer Pause Mode 24.3.3. Watchdog Timer Clocks 24.3.4. Watchdog Timer Resets 24.3.5. FPGA Interface
24.3.4. Watchdog Timer Resets
24.3.4.1. Taking the Watchdog Timer Out of Reset
24.4. Watchdog Timer Programming Model
24.4.1. Setting the Timeout Period Values 24.4.2. Selecting the Output Response Mode 24.4.3. Enabling and Initially Starting a Watchdog Timer 24.4.4. Reloading a Watchdog Counter 24.4.5. Pausing a Watchdog Timer 24.4.6. Disabling and Stopping a Watchdog Timer 24.4.7. Watchdog Timer State Machine
25. Introduction to the HPS Component
25.1. MPU Subsystem 25.2. Arm* CoreSight* Debug Components 25.3. Interconnect 25.4. HPS-to-FPGA Interfaces 25.5. Memory Controllers 25.6. Support Peripherals 25.7. Interface Peripherals 25.8. On-Chip Memories
26. Instantiating the HPS Component
26.1. FPGA Interfaces 26.2. Configuring HPS Clocks and Resets 26.3. Configuring Peripheral Pin Multiplexing 26.4. Configuring the External Memory Interface 26.5. Using the Address Span Extender Component 26.6. Generating and Compiling the HPS Component
26.1. FPGA Interfaces
26.1.1. General Interfaces 26.1.2. FPGA-to-HPS SDRAM Interface 26.1.3. DMA Peripheral Request 26.1.4. Interrupts 26.1.5. AXI Bridges
26.2. Configuring HPS Clocks and Resets
26.2.1. User Clocks 26.2.2. Reset Interfaces 26.2.3. PLL Reference Clocks 26.2.4. Peripheral FPGA Clocks
26.2.1. User Clocks
26.2.1.1. User Clock Parameters 26.2.1.2. Clock Frequency Usage
26.3. Configuring Peripheral Pin Multiplexing
26.3.1. Configuring Peripherals 26.3.2. Connecting Unassigned Pins to GPIO 26.3.3. Using Unassigned IO as LoanIO 26.3.4. Resolving Pin Multiplexing Conflicts 26.3.5. Peripheral Signals Routed to FPGA
26.4. Configuring the External Memory Interface
26.4.1. Selecting PLL Output Frequency and Phase
27. HPS Component Interfaces
27.1. Memory-Mapped Interfaces 27.2. Clocks 27.3. Resets 27.4. Debug and Trace Interfaces 27.5. Peripheral Signal Interfaces 27.6. Other Interfaces
27.1. Memory-Mapped Interfaces
27.1.1. FPGA-to-HPS Bridge 27.1.2. HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges 27.1.3. FPGA-to-HPS SDRAM Interface
27.1.1. FPGA-to-HPS Bridge
27.1.1.1. ACP Sideband Signals
27.2. Clocks
27.2.1. Alternative Clock Inputs to HPS PLLs 27.2.2. User Clocks 27.2.3. AXI Bridge FPGA Interface Clocks 27.2.4. SDRAM Clocks 27.2.5. Peripheral FPGA Clocks
27.3. Resets
27.3.1. HPS-to-FPGA Reset Interfaces 27.3.2. HPS External Reset Request 27.3.3. Peripheral Reset Interfaces
27.4. Debug and Trace Interfaces
27.4.1. Trace Port Interface Unit 27.4.2. FPGA System Trace Macrocell Events Interface 27.4.3. FPGA Cross Trigger Interface 27.4.4. Debug APB* Interface
27.5. Peripheral Signal Interfaces
27.5.1. DMA Controller Interface
27.6. Other Interfaces
27.6.1. MPU Standby and Event Interfaces 27.6.2. General Purpose Signals 27.6.3. FPGA-to-HPS Interrupts 27.6.4. Boot from FPGA Interface 27.6.5. Input-only General Purpose Interface
28. Simulating the HPS Component
28.1. Simulation Flows 28.2. Clock and Reset Interfaces 28.3. FPGA-to-HPS AXI Slave Interface 28.4. HPS-to-FPGA AXI Master Interface 28.5. Lightweight HPS-to-FPGA AXI Master Interface 28.6. FPGA-to-HPS SDRAM Interface 28.7. HPS-to-FPGA MPU Event Interface 28.8. Interrupts Interface 28.9. HPS-to-FPGA Debug APB* Interface 28.10. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 28.11. HPS-to-FPGA Cross-Trigger Interface 28.12. HPS-to-FPGA Trace Port Interface 28.13. FPGA-to-HPS DMA Handshake Interface 28.14. Boot from FPGA Interface 28.15. General Purpose Input Interface
28.1. Simulation Flows
28.1.1. Setting Up the HPS Component for Simulation 28.1.2. Generating the HPS Simulation Model in Platform Designer (Standard) 28.1.3. Running the Simulations
28.1.1. Setting Up the HPS Component for Simulation
28.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
28.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
28.1.1.1.1. Setting Up the HPS Component for Simulation
28.1.3. Running the Simulations
28.1.3.1. Running HPS RTL Simulation 28.1.3.2. Running HPS Post-Fit Simulation
28.1.3.2. Running HPS Post-Fit Simulation
28.1.3.2.1. Post-Fit Simulation Files 28.1.3.2.2. BFM API Hierarchy Format
28.2. Clock and Reset Interfaces
28.2.1. Clock Interface 28.2.2. Reset Interface
28.6. FPGA-to-HPS SDRAM Interface
28.6.1. HPS Memory Interface Simulation
A. Booting and Configuration
A.1. Boot Overview A.2. FPGA Configuration Overview A.3. Booting and Configuration Options A.4. Boot Definitions A.5. Boot ROM Flow A.6. Typical Preloader Boot Flow A.7. FPGA Configuration
A.4. Boot Definitions
A.4.1. Reset A.4.2. Boot ROM A.4.3. Boot Select A.4.4. Flash Memory Devices for Booting A.4.5. Clock Select A.4.6. I/O Configuration A.4.7. L4 Watchdog 0 Timer A.4.8. Preloader A.4.9. U-Boot Loader
A.4.3. Boot Select
A.4.3.1. Boot Source I/O Mapping
A.4.3.1. Boot Source I/O Mapping
A.4.3.1.1. Boot Source I/O Configuration
A.4.4. Flash Memory Devices for Booting
A.4.4.1. SD/MMC Flash Devices A.4.4.2. NAND Flash Devices A.4.4.3. Quad SPI Flash Devices
A.4.4.1. SD/MMC Flash Devices
A.4.4.1.1. Default Settings of the SD/MMC Controller A.4.4.1.2. CSEL Settings for the SD/MMC Controller
A.4.4.2. NAND Flash Devices
A.4.4.2.1. NAND Flash Driver Features Supported in the Boot ROM Code A.4.4.2.2. CSEL Settings for the NAND Controller
A.4.4.3. Quad SPI Flash Devices
A.4.4.3.1. Quad SPI Controller Default Settings A.4.4.3.2. Quad SPI Flash Delay Configuration A.4.4.3.3. Quad SPI Controller CSEL Settings
A.6. Typical Preloader Boot Flow
A.6.1. HPS State on Entry to the Preloader A.6.2. Shared Memory A.6.3. Loading the Preloader Image
A.7. FPGA Configuration
A.7.1. Full Configuration A.7.2. Partial Reconfiguration
1. Arria® V Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Clock Manager
4. Reset Manager
5. FPGA Manager
6. System Manager
7. Scan Manager
8. System Interconnect
9. HPS-FPGA Bridges
10. CoreSight* Debug and Trace
11. SDRAM Controller Subsystem
12. On-Chip Memory
13. NAND Flash Controller
14. SD/MMC Controller
15. Quad SPI Flash Controller
16. DMA Controller
17. Ethernet Media Access Controller
18. USB 2.0 OTG Controller
19. SPI Controller