Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

27.6. Generating and Compiling the HPS Component

The process of generating and compiling an HPS design is very similar to the process for any other Platform Designer (Standard) project. Perform the following steps:

  1. Generate the design with Platform Designer (Standard). The generated files include an .sdc file containing clock timing constraints. If simulation is enabled, simulation files are also generated.
  2. Add <system_name>.qip to the Quartus Prime project. <qsys_system_name>.qip is the Quartus Prime IP file for the HPS component, generated by Platform Designer (Standard).
  3. Perform analysis and synthesis with the Quartus Prime software.
  4. Assign constraints to the SDRAM component. When Platform Designer (Standard) generates the HPS component (step 1), it generates the pin assignment Tcl Script File (.tcl) to perform memory assignments. The script file name is <system_name>_pin_assignments.tcl, where <system_name> is the name of your Platform Designer (Standard) system. Run this script to assign constraints to the SDRAM component.
    Note: For information about running the pin assignment script, refer to “IP catalog” in the Implementing and Parameterizing Memory IP chapter in the External Memory Interface Handbook.

    You do not need to specify pin assignments other than memory assignments. When you configure pin multiplexing as described in Configuring Peripheral Pin Multiplexing section, you implicitly make pin assignments for all HPS peripherals. Each peripheral is routed exclusively to the pins you specify. HPS I/O signals are exported to the top level of the Platform Designer (Standard) design, with information enabling the Quartus Prime software to make pin assignments automatically.

    You can view and modify the assignments in the Peripheral Pin Multiplexing tab. You can also view the assignments in the Quartus fitter report.

  5. Compile the design with the Quartus Prime software.
  6. Optionally back-annotate the SDRAM pin assignments, to eliminate pin assignment warnings the next time you compile the design.