Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

21.4.7. DMA Controller Interface

The I2C controller supports DMA signaling to indicate when data is ready to be read or when the transmit FIFO needs data. This support requires 2 DMA channels, one for transmit data and one for receive data. The I2C controller supports both single and burst DMA transfers. System software can choose the DMA burst mode by programming an appropriate value into the threshold registers. The recommended setting of the FIFO threshold register value is half full.

To enable the DMA controller interface on the I2C controller, you must write to the DMA control register (DMACR) bits. Writing a 1 into the TDMAE bit field of DMACR register enables the I2C controller transmit handshaking interface. Writing a 1 into the RDMAE bit field of the DMACR register enables the I2C controller receive handshaking interface. †