Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

21.5.2.1. Initial Configuration

For master mode operation, the target address and address format can be changed dynamically without having to disable the I2C controller. This feature is only applicable when the I2C controller is acting as a master because the slave requires the component to be disabled before any changes can be made to the address. To use the I2C controller as a master, perform the following steps: †

For multiple I2C transfers, perform additional writes to the Tx FIFO such that the Tx FIFO does not become empty during the I2C transaction. IF the Tx FIFO is completely emptied at any stage, then the master stalls the transfer by holding the SCL line low because there was no stop bit indicating the master to issue a STOP. The master completes the transfer when it finds a Tx FIFO entry tagged with a Stop bit.

  1. Disable the I2C controller by writing 0 to bit 0 of the IC_ENABLE register. †
  2. Write to the IC_CON register to set the maximum speed mode supported for slave operation (bits 2:1) and to specify whether the I2C controller starts its transfers in 7/10 bit addressing mode when the device is a slave (bit 3). †
  3. Write to the IC_TAR register the address of the I2C device to be addressed. It also indicates whether a General Call or a START BYTE command is going to be performed by I2C. The desired speed of the I2C controller master-initiated transfers, either 7-bit or 10-bit addressing, is controlled by the IC_10BITADDR_MASTER bit field (bit 12). †
  4. Enable the I2C controller by writing a 1 in bit 0 of the IC_ENABLE register. †
  5. Now write the transfer direction and data to be sent to the IC_DATA_CMD register. If the IC_DATA_CMD register is written before the I2C controller is enabled, the data and commands are lost as the buffers are kept cleared when the I2C controller is not enabled. †