Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

2.2.9. CoreSight Debug and Trace

The CoreSight debug and trace system offers the following features:
  • Real-time program flow instruction trace through a separate PTM for each processor
  • Host debugger JTAG interface
  • Connections for cross-trigger and STM-to-FPGA interfaces, which enable soft IP cores to generate of triggers and system trace messages
  • Custom message injection through STM into trace stream for delivery to host debugger
  • Capability to route trace data to any slave accessible to the ETR master, which is connected to the level 3 (L3) interconnect