Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

21.4.5. Clock Frequency Configuration

When you configure the I2C controller as a master, the SCL count registers must be set before any I2C bus transaction can take place in order to ensure proper I/O timing. † There are four SCL count registers:

  • Standard speed I2C clock SCL high count, IC_SS_SCL_HCNT
  • Standard speed I2C clock SCL low count, IC_SS_SCL_LCNT
  • Fast speed I2C clock SCL high count, IC_FS_SCL_HCNT
  • Fast speed I2C clock SCL low count, IC_FS_SCL_LCNT

It is not necessary to program any of the SCL count registers if the I2C controller is enabled to operate only as an I2C slave, since these registers are used only to determine the SCL timing requirements for operation as an I2C master. †