Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

5.3.1.2. Monitor

The monitor block is an instance of the Synopsys* GPIO IP (DW_apb_gpio), which is a separate instance of the IP that comprises the three HPS GPIO interfaces. The monitor block connects to the configuration signals in the FPGA. This block monitors key signals related to FPGA configuration such as INIT_DON E, CRC_ERROR, and PR_DONE. Software configures the monitor block through the register slave interface, and can either poll FPGA signals or be interrupted. The mon address map within the FPGA manager register address map contains the monitor registers. For more information about FPGA manager registers, refer to FPGA Manager Address Map and Register Definitions

You can program the FPGA manager to treat any of the monitor signals as interrupt sources. Independent of the interrupt source type, the monitor block always drives an active-high level interrupt to the MPU. Each interrupt source can be of the following types:

  • Active-high level
  • Active-low level
  • Rising edge
  • Falling edge