Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

21. I2C Controller

The I2C controller provides support for a communication link between integrated circuits on a board. It is a simple two-wire bus which consists of a serial data line (SDA) and a serial clock (SCL) for use in applications such as temperature sensors and voltage level translators to EEPROMs, A/D and D/A converters, CODECs, and many types of microprocessors. †

The hard processor system (HPS) provides four I2C controllers to enable system software to communicate serially with I2C buses. Each I2C controller can operate in master or slave mode, and support standard mode of up to 100 Kbps or fast mode of up to 400 Kbps. These I2C controllers are instances of the Synopsys* DesignWare* APB* I2C (DW_apb_i2c) controller.

Each I2C controller must be programmed to operate in either master or slave mode only. Operating as a master and slave simultaneously is not supported. † 61

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†Paragraphs marked with the dagger (†) symbol are Synopsys* Proprietary. Used with permission.