Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

24.5. Timer Address Map and Register Definitions

The address map and register definitions for the HPS-FPGA bridges consist of the following regions:

  • OSC1 Timer Module 0
  • OSC1 Timer Module 1
  • SP Timer Module 0
  • SP Timer Module 1